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The Trenz Electronic TE0807 is an industrial-grade MPSoC SoM integrating a Xilinx an AMD Zynq UltraScale+ MPSoC, up to 8 GBytes of DDR4 SDRAM via 64bit 64 bit wide data bus, max. 512 MByte Flash memory for configuration and operation, 20 Gigabit transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os are provided via rugged high-speed stacking connections. All this in a compact 5.2 x 7.6 cm form factor, at the competitive price.

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  • MPSoC: ZYNQ UltraScale+ ZU7EV 900-pin package
  • Memory
    - 64bit 64 bit DDR4, 8 GByte maximum
    - Dual SPI boot Flash in parallel, 512 MByte maximum
  • User I/Os
    - 65 x PS MIOs, 48 x PL HD GPIOs,  156 x PL HP GPIOs (3 banks)
    - Serial transceivers: 4 x GTR + 16 x GTH
    - Transceiver clocks inputs and outputs
    - PLL clock generator inputs and outputs
  • Si5345 - 10 output PLL
  • All power supplies on board, single 3.3V power source required
    - LPD, FPD, PL separately controlled power domains
  • Support for all boot modes (except NAND) and scenarios
  • Support for any combination of PS connected peripherals
  • Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
  • B2B connectors: 4 x 160 pin

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titleFigure 1: TE0807-02 03 block diagram


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Main Components

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titleFigure 2: TE0807-02 03 main components


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  1. AMD Xilinx ZYNQ UltraScale+ ZU7EV-1FBVB900 MPSoC, U1
  2. EN63A0QI 12A MPQ8633B 20 A PowerSoC DC-DC converter, U4
  3. TI TPS72018 LDO @1.8V, U6
  4. TI TPS74401 LDO @0.9V, U14
  5. TI TPS74401 LDO @1.2V, U28TI TPS72018 LDO @1.8V, U6
  6. Clock, U5
  7. Quarz Crystal @50.000MHz, Y1
  8. Low-power programmable oscillator @ 25.000000 MHz (IN0 for U5), U25
  9. TI TPS74801 LDO @1.8V, U10
  10. TI TPS74801 LDO @0.9V, U8
  11. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U12
  12. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U9
  13. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U2
  14. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U3
  15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
  16. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
  17. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
  18. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
  19. 1.8V, 512 Mbit QSPI flash memory ,U17
  20. 1.8V, 512 Mbit QSPI flash memory, U7
  21. TI TPS72018 LDO @1.8V, U27

 

Initial Delivery State

 Storage Device Name

Content

Notes

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor.

SPI Flash Quad Enable bit

Programmed

-

SPI Flash main array

Not programmed

-

eFUSE USER

Not programmed

-

eFUSE Security

Not programmed

-
Si5345A OTP NVMNot programmed-

...

Table 4: B2B connector pin-outs of available PL and PS banks of the TE0807-02 03 SoM.

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

...

The configuration of the I/O's MIO13 - MIO77 are depending on the base-board peripherals connected to these pins.

MGT Lanes

The Xilinx AMD Zynq UltraScale+ MPSoC device used on the TE0807 module has 20 high-speed data lanes (Xilinx AMD GTH / GTR transceiver). All of them are wired directly to B2B connector. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

BankTypeLaneSignal NameB2B PinFPGA Pin
224GTH0
  • B224_RX0_P
  • B224_RX0_N
  • B224_TX0_P
  • B224_TX0_N
  • J1-69
  • J1-71
  • J1-68
  • J1-70
  • MGTHRXP0_224, V2
  • MGTHRXN0_224, V1
  • MGTHTXP0_224, W4
  • MGTHTXN0_224, W3
1
  • B224_RX1_P
  • B224_RX1_N
  • B224_TX1_P
  • B224_TX1_N
  • J1-63
  • J1-65
  • J1-62
  • J1-64
  • MGTHRXP1_224, U4
  • MGTHRXN1_224, U3
  • MGTHTXP1_224, V6
  • MGTHTXN1_224, V5
2
  • B224_RX2_P
  • B224_RX2_N
  • B224_TX2_P
  • B224_TX2_N
  • J1-57
  • J1-59
  • J1-56
  • J1-58
  • MGTHRXP2_224, T2
  • MGTHRXN2_224, T1
  • MGTHTXP2_224, T6
  • MGTHTXN2_224, T5
3
  • B224_RX3_P
  • B224_RX3_N
  • B224_TX3_P
  • B224_TX3_N
  • J1-51
  • J1-53
  • J1-50
  • J1-52
  • MGTHRXP3_224, P2
  • MGTHRXN3_224, P1
  • MGTHTXP3_224, R4
  • MGTHTXN3_224, R3
225GTH0
  • B225_RX0_P
  • B225_RX0_N
  • B225_TX0_P
  • B225_TX0_N
  • J1-45
  • J1-47
  • J1-44
  • J1-46
  • MGTHRXP0_225, N4
  • MGTHRXN0_225, N3
  • MGTHTXP0_225, P6
  • MGTHTXN0_225, P5
1
  • B225_RX1_P
  • B225_RX1_N
  • B225_TX1_P
  • B225_TX1_N
  • J1-39
  • J1-41
  • J1-38
  • J1-40
  • MGTHRXP1_225, M2
  • MGTHRXN1_225, M1
  • MGTHTXP1_225, M6
  • MGTHTXN1_225, M5
2
  • B225_RX2_P
  • B225_RX2_N
  • B225_TX2_P
  • B225_TX2_N
  • J1-33
  • J1-35
  • J1-32
  • J1-34
  • MGTHRXP2_225, K2
  • MGTHRXN2_225, K1
  • MGTHTXP2_225, L4
  • MGTHTXN2_225, L3
3
  • B225_RX3_P
  • B225_RX3_N
  • B225_TX3_P
  • B225_TX3_N
  • J1-27
  • J1-29
  • J1-26
  • J1-28
  • MGTHRXP3_225, J4
  • MGTHRXN3_225, J3
  • MGTHTXP3_225, K6
  • MGTHTXN3_225, K5
226GTH0
  • B226_RX0_P
  • B226_RX0_N
  • B226_TX0_P
  • B226_TX0_N
  • J1-21
  • J1-23
  • J1-20
  • J1-22
  • MGTHRXP0_226, H2
  • MGTHRXN0_226, H1
  • MGTHTXP0_226, H6
  • MGTHTXN0_226, H5
1
  • B226_RX1_P
  • B226_RX1_N
  • B226_TX1_P
  • B226_TX1_N
  • J1-15
  • J1-17
  • J1-14
  • J1-16
  • MGTHRXP1_226, G4
  • MGTHRXN1_226, G3
  • MGTHTXP1_226 G8
  • MGTHTXN1_226, G7
2
  • B226_RX2_P
  • B226_RX2_N
  • B226_TX2_P
  • B226_TX2_N
  • J1-9
  • J1-11
  • J1-8
  • J1-10
  • MGTHRXP2_226, F2
  • MGTHRXN2_226, F1
  • MGTHTXP2_226, F6
  • MGTHTXN2_226, F5
3
  • B226_RX3_P
  • B226_RX3_N
  • B226_TX3_P
  • B226_TX3_N
  • J1-3
  • J1-5
  • J1-2
  • J1-4
  • MGTHRXP3_226, E4
  • MGTHRXN3_226, E3
  • MGTHTXP3_226, E8
  • MGTHTXN3_226, E7
227GTH0
  • B227_TX0_P
  • B227_TX0_N
  • B227_RX0_P
  • B227_RX0_N
  • J2-45
  • J2-43
  • J2-48
  • J2-46
  • MGTHRXP0MGTHTXP0_227, D1D6
  • MGTHRXN0MGTHTXN0_227, D2D5MGTHTXP0
  • MGTHRXP0_227, D5D2
  • MGTHTXN0MGTHRXN0_227, D6D1
1
  • B227_TX1_P
  • B227_TX1_N
  • B227_RX1_P
  • B227_RX1_N
  • J2-39
  • J2-37
  • J2-42
  • J2-40
  • MGTHRXP1MGTHTXP1_227, C3C8
  • MGTHRXN1MGTHTXN1_227, C4C7MGTHTXP1
  • MGTHRXP1_227, C7C4
  • MGTHTXN1MGTHRXN1_227, C8C3
2
  • B227_TX2_P
  • B227_TX2_N
  • B227_RX2_P
  • B227_RX2_N
  • J2-33
  • J2-31
  • J2-36
  • J2-34
  • MGTHRXP2MGTHTXP2_227, B1B6
  • MGTHRXN2MGTHTXN2_227, B2B5MGTHTXP2
  • MGTHRXP2_227, B5B2
  • MGTHTXN2MGTHRXN2_227, B6B1
3
  • B227_TX3_P
  • B227_TX3_N
  • B227_RX3_P
  • B227_RX3_N
  • J2-27
  • J2-25
  • J2-30
  • J2-28
  • MGTHRXP3MGTHTXP3_227, A3A8
  • MGTHRXN3MGTHTXN3_227, A4A7MGTHTXP3
  • MGTHRXP3_227, A7A4
  • MGTHTXN3MGTHRXN3_227, A8A3
505GTR0
  • B505_TX0_P
  • B505_TX0_N
  • B505_RX0_P
  • B505_RX0_N
  • J2-69
  • J2-67
  • J2-72
  • J2-70
  • PS_MGTRRXP0MGTRTXP0_505, M27
  • PS_MGTRRXN0MGTRTXN0_505, M28
  • PS_MGTRTXP0MGTRRXP0_505, L29
  • PS_MGTRTXN0MGTRRXN0_505, L30
1
  • B505_TX1_P
  • B505_TX1_N
  • B505_RX1_P
  • B505_RX1_N
  • J2-63
  • J2-61
  • J2-66
  • J2-64
  • PS_MGTRRXP1MGTRTXP1_505, K27
  • PS_MGTRRXN1MGTRTXN1_505, K28
  • PS_MGTRTXP1MGTRRXP1_505, J29
  • PS_MGTRTXN1MGTRRXN1_505, J30
2
  • B505_TX2_P
  • B505_TX2_N
  • B505_RX2_P
  • B505_RX2_N
  • J2-57
  • J2-55
  • J2-60
  • J2-58
  • PS_MGTRRXP2MGTRTXP2_505, J25
  • PS_MGTRRXN2MGTRTXN2_505, J26
  • PS_MGTRTXP2MGTRRXP2_505, H27
  • PS_MGTRTXN2MGTRRXN2_505, H28
3
  • B505_TX3_P
  • B505_TX3_N
  • B505_RX3_P
  • B505_RX3_N
  • J2-51
  • J2-49
  • J2-54
  • J2-52
  • PS_MGTRRXP3MGTRTXP3_505, G25
  • PS_MGTRRXN3MGTRTXN3_505, G26
  • PS_MGTRTXP3MGTRRXP3_505, G29
  • PS_MGTRTXN3MGTRRXN3_505, G30

Table 5: MGT lanes

...

Clock signalBankSourceFPGA PinNotes
B224_CLK0_P224B2B, J3-62MGTREFCLK0P_224, R8Supplied by the carrier board
B224_CLK0_N224B2B, J3-60MGTREFCLK0N_224, R7Supplied by the carrier board
B224_CLK1_P224U5, CLK4_PMGTREFCLK1P_224, N8On-board Si5345A
B224_CLK1_N224U5, CLK4_NMGTREFCLK1N_224, N7On-board Si5345A
B225_CLK0_P225B2B, J3-67MGTREFCLK0P_225, L8Supplied by the carrier board
B225_CLK0_N225B2B, J2J3-65MGTREFCLK0N_225, L7Supplied by the carrier board
B225_CLK1_P225U5, CLK3_PMGTREFCLK1P_225, J8On-board Si5345A
B225_CLK1_N225U5, CLK3_NMGTREFCLK1N_225, J7On-board Si5345A
B226_CLK0_P226U5, CLK2_PMGTREFCLK0P_226, H10On-board Si5345A
B226_CLK0_N226U5, CLK2_NMGTREFCLK0N_226, H9On-board Si5345A
B226_CLK1_P226B2B, J3-61MGTREFCLK1P_226, F10Supplied by the carrier board
B226_CLK1_N226B2B, J3-59MGTREFCLK1N_226, F9Supplied by the carrier board
B227_CLK0_P227U5, CLK1_PMGTREFCLK0P_227, D10On-board Si5345A
B227_CLK0_N227U5, CLK1_NMGTREFCLK0N_227, D9On-board Si5345A
B227_CLK1_P227B2B, J2-22MGTREFCLK1P_227, B10Supplied by the carrier board
B227_CLK1_N227B2B, J2-24MGTREFCLK1N_227, B9Supplied by the carrier board
B505_CLK0_P505B2B, J2-10PS_MGTREFCLK0P_505, M23Supplied by the carrier board
B505_CLK0_N505B2B, J2-12PS_MGTREFCLK0N_505, M24Supplied by the carrier board
B505_CLK1_P505B2B, J2-16PS_MGTREFCLK1P_505, L25Supplied by the carrier board
B505_CLK1_N505B2B, J2-18PS_MGTREFCLK1N_505, L26Supplied by the carrier board
B505_CLK2_P505U5, CLK5_PPS_MGTREFCLK2P_505, K23On-board Si5345A
B505_CLK2_N505U5, CLK5_NPS_MGTREFCLK2N_505, K24On-board Si5345A
B505_CLK3_P505U5, CLK6_PPS_MGTREFCLK3P_505, H23On-board Si5345A
B505_CLK3_N505U5, CLK6_NPS_MGTREFCLK3N_505, H24On-board Si5345A

...

Configuration Bank Control Signals

The Xilinx AMD Zynq UltraScale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B connector J2.

For further information about the particular control signals and how to use and evaluate them, refer to the  Xilinx AMD Zynq UltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.

SignalB2B Connector PinFunction
DONEJ2-116PL configuration completed.
PROG_BJ2-100PL configuration reset signal.
INIT_BJ2-98PS is initialized after a power-on reset.
SRST_BJ2-96System reset.
MODE0 ... MODE3J2-109/J2-107/J2-105/J2-103

4-bit boot mode pins.

For further information about the boot modes refer to the Xilinx AMD Zynq UltraScale+ MPSoC TRM section 'Boot and Configuration'.

ERR_STATUS / ERR_OUTJ2-86 / J2-88

ERR_OUT signal is asserted for accidental loss of power, an error, or an exception in the MPSoC's Platform Management Unit (PMU).

ERR_STATUS indicates a secure lock-down state.

PUDC_BJ2-127Pull-up during configuration (pulled-up to PL_1V8).

Table 8: B2B connector pin-out of MPSoC's PS configuration bank.

Analog Input

The Xilinx AMD Zynq UltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.

...

PS MIOFunctionConnected to
0SPI0U7-B2, CLK
1SPI0U7-D2, DO/IO1
2SPI0U7-C4, WP/IO2
3SPI0U7-D4, HOLD/IO3
4SPI0U7-D3, DI/IO0 
5SPI0 U7-C2, CS
6N/ANot connected
7SPI1U17-C2, CS
8SPI1U17-D3, DI/IO0
9SPI1U17-D2, DO/IO1
10SPI1U17-C4, WP/IO2
11SPI1U17-D4, HOLD/IO3
12SPI1U17-B2, CLK
13 ... 77user dependentB2B connector J2

Table 11: TE0807-02 03 PS MIO mapping

On-board Peripherals

...

 NameICDesignatorPS7MIONotes
SPI FlashN25Q512A11G1240EMT25QU512ABB8E12-0SITU7QSPI0MIO0 ... MIO5dual parallel booting possible, 64 MByte memory per Flash IC at standard configuration
SPI FlashN25Q512A11G1240EMT25QU512ABB8E12-0SITU17QSPI0MIO7 ... MIO12

Table 12: Peripherals connected to the PS MIO pins.

DDR4 SDRAM

The TE0807-02 03 SoM is equipped with with four DDR4 -2400 SDRAM modules chips with a total of up to 8 GByte memory density. The SDRAM modules chips are connected to the Zynq the Zynq MPSoC's PS DDR controller (bank 504) with a 64bit 64 bit wide data bus.

Refer to the Xilinx AMD Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s.

...

SignalB2B Connector PinFunction
PLL_FINCJ2-81Frequency increment
PLL_LOLNJ2-85Loss of lock (active-low)
PLL_SEL0 / PLL_SEL1J2-93 / J2-87Manual input switching
PLL_FDECJ2-94Frequency decrement
PLL_RSTJ2-89

Device reset (active-low)

PLL_SCL / PLL_SDAJ2-90 / J2-92

I2C interface, external pull-ups needed for SCL / SDA lines

I2C address in current configuration: 1101000b1101001b.

Table 14: B2B connector pin-out of Si5345A programmable clock generator.

...

Si5345 OTP can only be programmed two times, as different user configurations may required different setup TE0808 TE0807 is normally shipped with blank OTP.
For more information refer to Si5345 at SiLabs.

Oscillators

The TE0808TE0807-04 SoM is equipped with two on-board oscillators to provide the Zynq's MPSoC's PS configuration bank 503 with reference clock signals.

...

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx AMD provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

...

The TE0807 module equipped with the Xilinx AMD Zynq UltraScale+  MPSoC MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

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titleFigure 3: TE0807-02 03 Power Distribution Diagram


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See also Xilinx AMD datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0807 module.

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The TE0807 SoM meets the recommended criteria to power up the Xilinx AMD Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.

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titleFigure 4: TE0807-02 03 Power-on Sequence Diagram


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The control signals have to be asserted on the B2B connector J2, whereby some of the Power-Good signals need external pull-up resistors.

TPS82085SIL 4K76VTPS82085SIL
Enable-SignalB2B Connector PinMax. VoltageNote
Power-Good-SignalB2B Connector PinPull-up ResistorNote
EN_LPDJ2-1086V6.5VMPM3834CGPA data sheet
LP_GOODJ2-1064K7, pulled up to LP_DCDC-
EN_FPDJ2-102DCDCINNC7S08P5X data sheet
PG_FPDJ2-1104K7, pulled up to DCDCIN-
EN_PLJ2-101PL_DCINleft floating for logic high
(drive to GND for logic low)

PG_PLJ2-10410K, pulled up to PL_DCIN

-

EN_DDRJ2-112DCDCINNC7S08P5X data sheet
PG_DDRJ2-1144K7, pulled up to DCDCIN-
EN_PSGTJ2-84DCDCINNC7S08P5X data sheet
PG_PSGTJ2-82External pull-up needed (max. 5.5V),
max. sink current 1 mA
TPS74801 data sheet
EN_GT_RJ2-95GT_DCDCNC7S08P5X data sheet
PG_GT_RJ2-91External pull-up needed (max. 5.5V),
max. sink current 1 mA
TPS74401 data sheet
EN_PLL_PWRJ2-776.5VMPM3834CGPA data sheet
PG_PLL_1V8J2-80External pull-up needed (max. 5.5V),
max. sink current 1 mA
10K, pulled up to GT_DCDCTPS82085SIL data sheet

Table 18: Recommended operation conditions of DC-DC converter control signals.

...

It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are high, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx AMD datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0808 TE0807 SoM.

Voltage Monitor Circuit

...

Power Rail Name

B2B J1 PinsB2B J2 PinsB2B J3 PinsB2B J4 Pins

Directions

Note
PL_DCIN151, 153, 155, 157, 159---Input-
DCDCIN

-

154, 156, 158, 160,
153, 155, 157, 159

--Input-
LP_DCDC-138, 140, 142, 144--Input-
PS_BATT-125--Input-
GT_DCDC--157, 158, 159, 160-Input-
PLL_3V3--152-InputU5 (programmable PLL)
3.3V nominal input
SI_PLL_1V8--151-OutputInternal voltage level
1.8V nominal output
PS_1V8-99147, 148-Output

Internal voltage level
1.8V nominal output

PL_1V891, 121---Output

Internal voltage level
1.8V nominal output

DDR_1V2-135--Output

Internal voltage level
1.2V nominal output

VCCO47--43, 44-Input-
VCCO48--15, 16-Input-
VCCO64---58, 106Input-
VCCO65---69, 105Input-
VCCO6690, 120---Input-

Table 19: TE0807-02 03 power rails

Bank Voltages

BankTypeSchematic NameVoltageReference Input VoltageVoltage Range
47HDVCCO47user-1.2V to 3.3V
48HDVCCO48user-1.2V to 3.3V
64HPVCCO64userVREF_64, pin J4-881.2V to 1.8V
65HPVCCO65userVREF_65, pin J4-151.2V to 1.8V
66HPVCCO66userVREF_66, pin J1-1081.2V to 1.8V
500MIOPS_1V81.8V--
501MIOPS_1V81.8V--
502MIOPS_1V81.8V--
503CONFIGPS_1V81.8V--

Table 20: TE0807-02 03 I/O bank voltages

See Xilinx AMD Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.

...

Parameter

MinMax

Unit

Notes / Reference Document

PL_DCIN-0.374.5VTPS82085SIL / EN63A0QI MPQ8633B data sheet
DCDCIN-0.376.5VTPS82085SIL / TPS51206 MPM3834CGPA data sheet
LP_DCDC-0.34VTPS3106K33DBVR data sheet
GT_DCDC-0.376VTPS82085SIL TPS74401RGW data sheet
PS_BATT-0.52VXilinx AMD DS925 data sheet
PLL_3V3-0.53.8VSi5345/44/42 data sheet
VCCO for HD I/O banks-0.53.4VXilinx AMD DS925 data sheet
VCCO for HP I/O banks-0.52VXilinx AMD DS925 data sheet
I/O input voltage for HD I/O banks-0.55VCCO + 0.55VXilinx AMD DS925 data sheet
I/O input voltage for HP I/O banks-0.55VCCO + 0.55VXilinx AMD DS925 data sheet
PS I/O input voltage (MIO pins)-0.5VCCO_PSIO + 0.55VXilinx AMD DS925 data sheet,
VCCO_PSIO 1.8V nominally
PS GTR reference clocks absolute input voltage-0.51.1VXilinx AMD document DS925
PS GTR absolute input voltage-0.51.1VXilinx AMD document DS925
MGT clock absolute input voltage-0.51.3VXilinx AMD document DS925

MGT Receiver (RXP/RXN) and transmitter
(TXP/TXN) absolute input voltage

-0.51.2VXilinx AMD DS925 data sheet

Voltage on input pins of
NC7S08P5X 2-Input AND Gate

-0.5VCC + 0.5VNC7S08P5X data sheet,
see schematic for VCC

Voltage on input pins (nMR) of
TPS3106K33DBVR Voltage Monitor, U41

-0.3VDD + 0.3V

TPS3106 data sheet,
VDD = LP_DCDC

"Enable"-signals on TPS82085SIL
(EN_PLL_PWR, EN_LPD)
-0.37VTPS82085SIL data sheet

Storage temperature (ambient)

-40

100

°C

ROHM Semiconductor SML-P11 Series data sheet

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TPS82085SIL / TPS51206PSQ data sheet
ParameterMinMaxUnitNotes / Reference Document
PL_DCIN3.363.399VEN63A0QI / TPS82085SIL data sheetDCDCIN
DCDCIN3.363.465V
LP_DCDC3.33.6399VTPS82085SIL / TPS3106 data sheet
GT_DCDC3.363.399VTPS82085SIL data sheet
PS_BATT1.21.5VXilinx AMD DS925 data sheet
PLL_3V33.33.47VSi5345/44/42 data sheet
3.3V typical
VCCO for HD I/O banks1.143.4VXilinx AMD DS925 data sheet
VCCO for HP I/O banks0.951.9VXilinx AMD DS925 data sheet
I/O input voltage for HD I/O banks.-0.2VCCO + 0.2VXilinx AMD DS925 data sheet
I/O input voltage for HP I/O banks-0.2VCCO + 0.2VXilinx AMD DS925 data sheet
PS I/O input voltage (MIO pins)-0.2VCCO_PSIO + 0.2VXilinx AMD DS925 data sheet,
VCCO_PSIO 1.8V nominally
PL bank reference voltage VREF pin-0.52VXilinx AMD DS925 data sheet
Voltage on input pins of
NC7S08P5X 2-Input AND Gate
0VCCV

NC7S08P5X data sheet,
see schematic for VCC

Voltage on input pin 'MR' of
TPS3106K33DBVR Voltage Monitor, U41

0VDDV

TPS3106 data sheet,
VDD = LP_DCDC

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Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Note
See Xilinx AMD datasheet DS925 for more information about absolute maximum and recommended operating ratings for the Zynq UltraScale+ chips.

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  • Module size: 52 mm × 76 mm.  Please download the assembly diagram for exact numbers

  • Mating height with standard connectors: 4mm5 mm

  • PCB thickness: 1.6mm7 mm

  • Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

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Hardware Revision History

02
DateRevision

Notes

PCN LinkDocumentation Link
2024-07-010204current available module revisionPCN-20240514 TE0807-03 to TE0807-04 Hardware Revision ChangeTE0807-04
2020-06-0501first production release-TE0807-01

Table 23: Hardware revision history table

03current available module revisionPCN-20200511TE0807-03
-02current available module revision-TE0807-02
-01first production release-TE0807-01

Table 23: Hardware revision history table


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Document Change History

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Date

Revision

Contributors

Description

Page info
modified-date
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  • Updated to REV04

2023-07-12

v.29

Markus Kirberg

  • Correction on MGT Lanes (column "FPGA Pin" of bank 227 and 505 was incorrect)

2021-09-07

  • Correction on Power section
2021-06-10v.27John Hartfiel
  • correction number IOs in BD
2021-05-17v.26John Hartfiel
  • typo correction in DDR section
2021-05-03v.25Martin Rohrmüller
  • Updated to REV03

2021-03-11

v.24

Antti Lukats

  • Corrected B2B include macro

2019-06-14

v.22John Hartfiel
  • typo correction SI5345 I2C address
  • typo B2B Pin of CLK signals

2018-08-07

v.20Ali Naseri
  • initial document

Table 24: Document change history

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