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Overview

The Trenz Electronic TEBA0841 is a low cost carrier board for testing, evaluation and development purposes of the TE0841 and TE0741 modules. Although this base-board is dedicated to the modules TE0841 and TE0741, it is also compatible with other Trenz Electronic 4 x 5 cm SoMs. The carrier board offers one SFP connector, one Micro USB2 B connector, two 2x25-pin headers and one XMOD header to get access to the I/O's and interfaces of FPGA modules. To test and evaluate the Multi-gigabit transceiver units of the FPGA module, 6 MGT lanes on the carrier board are routed in a loop-back circuit on the B2B connectors.

See page "4 x 5 cm carriers" to get information about the SoMs supported by the TEBA0841 carrier board.

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Refer to http://trenz.org/teba0841-info for the current online version of this manual and other available documentation.

Key Features

• SFP+ connector (Enhanced small form-factor pluggable), supports data transmission rates up to 10 Gbit/s
• Micro USB2 Type B Connector
• Trenz Electronic 4x5 module B2B connectors (3 x Samtec LSHM series connectors)
• 4 x 5 SoM programmable by XMOD header
  
• Soldering-pads for pin headers for access to SoM's I/O-bank pins, usable as LVDS-pairs
• Soldering-pads for pin headers for access to further interfaces and I/O's of the SoM
• 2 x user LEDs routed to I/O-pins of the SoM
• 4-bit DIP switch for setting module parameters
• 4x VCCIO selection jumper to set module's bank voltages
  
  

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Main Component

1. Samtec Razor Beam™ LSHM-150 B2B connector, JB1
2. Samtec Razor Beam™ LSHM-150 B2B connector, JB3
3. Samtec Razor Beam™ LSHM-130 B2B connector, JB2
4. 6-pin header J26, for selecting PL I/O-bank voltage
5. 6-pin header J5, for selecting PL I/O-bank voltage
6. 6-pin header J6, for selecting PL I/O-bank voltage
7. 6-pin header J27, for selecting PL I/O-bank voltage
8. Micro USB2 Type B connector J10 (Device or OTG mode)
9. 2-pin VBAT header J7
10. XMOD FTDI JTAG/UART header, JX1
11. 4-bit DIP-switch S1
12. User LED D1 (green)
13. User LED D2 (red)
14. 10-pin header soldering-pads J4, 6 I/O's available
15. 16-pin header soldering-pads J3, JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible pin-assignment)
16. 50-pin header soldering-pads J17, for access to PL I/O-bank pins (42 I/O'S, 21 LVDS pairs)
17. 50-pin header soldering-pads J20, for access to PL I/O-bank pins (42 I/O'S, 21 LVDS pairs)
18. SFP+ Connector, J1

Initial Delivery State

Board is shipped in following configuration:

• VCCIO selection jumpers are all set to 1.8 V
• Pin headers (not soldered to the board, but included in the package as separate component)

Different delivery configurations are available upon request.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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B2B Connectors

Following table gives a summary of the available I/O's, interfaces and differential pairs of the mounted SoM on the B2B connectors JB1, JB2 and JB3 of the carrier board:

Table 1: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors

On-board Pin Header

The TEBA0841 carrier board has footprints as soldering pads to mount 2.54mm grid size pin headers to get access the PL I/O-bank's pins and further interfaces of the mounted SoM. With these pin headers, SoM's PL-I/O's are available to the user, a large quantity of these I/O's are also usable as  differential pairs.

Following table gives a summary of the pin-assignment, available interfaces and functional I/O's of the pin headers:

Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors

SFP+ Connector

The TEBA0841 carrier board is equipped with one SFP+ connector J1 (board-rev. 01: Molex 74441-0001). The connector is fitted into a SFP cage J2 (board-rev. 01: Molex 74737-0009).

The differential RX/TX data lanes are connected to B2B connector JB2, the control-lines are connected to B2B connector JB1.

Following table describes the pin-assignment of the SFP+ connector:

Table 3: SFP+ connector pin-assignment

Loop Back Circuits on B2B Connector JB1 and JB2

The TEBA0841 carrier board is mainly designed for the 4 x 5 SoMs TE0841 and TE0741. This SoMs have GTX-Transceiver units on the FPGA devices with up to 8 available MGT lanes. To test this MGT lanes, 6 RX/TX differential pairs are routed in loop back circuit on-board, hence the transmitted data on those MGT lanes flows back to its source in a loop back circuit without processing or modification.

The MGT lane pins are routed on-board as follows, if 4 x 5 SoM TE0841 is mounted on carrier board:

Table 4: Looped-backed MGT-lanes for mounted 4 x 5 SoM TE0841

JTAG Interface

JTAG access to the mounted SoM is provided through B2B connector JB3 and is routed to the XMOD header JX1 and also to pin header J3. With the TE0790 XMOD USB2 to JTAG adapter, the FPGA device of the mounted SoM can be programed via USB2 interface.

Table 5: JTAG interface signals

XMOD FTDI JTAG-Adapter Header JX1

The JTAG interface of the mounted SoM can be accessed via XMOD header JX1, so in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB2 interface. The TE0790 board provides also an UART interface to the SoM's FPGA device which can be accessed by the USB2 interface of the adapter-board while the signals between these serial interfaces will be converted.

Following table describes the signals and interfaces of the XMOD header JX1:

Table 6: XMOD header JX1 signals and connections

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the on-boards 3.3V supply voltage. Set the XMOD DIP-switch with the setting:

Table 7: XMOD adapter board DIP-switch positions for voltage configuration

JTAG/UART Header J3

As alternative to the XMOD header JX1, on the carrier board pin header J3 is present, which has a XMOD header-compatible pin-assignment, but also two additional pins (15,16) as differential pair to supply the mounted SoM with an external MGT reference clock signal:

Table 8: JTAG/UART header J3 signals and connections

UART Interface

UART interface is available on B2B connector JB1 established by the mounted SoM's FPGA device. With the TE0790 XMOD USB2 adapter, the UART signals can be converted to USB2 interface signals:

Table 9: UART interface signals

USB2 Interface

TEBA0841 board has one physical Micro USB2 Type B socket J10, the differential data signals of the USB2 socket are routed to the B2B connector JB2, where they can be accessed by the corresponding USB2 PHY transceiver of the mounted SoM, if available.

With Micro USB2 Type B connector, the USB2 interface is usable in Device or OTG mode.

Following table gives an overview of the USB2 interface signals:

Table 10: USB2 interface signals and connections

On-board Peripherals

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On-board LEDs

The on-board LEDs are available to the user and can be used to indicate system status and activities:

Table 11: On-board LEDs

DIP-Switch

There are one 4-bit DIP-witches S1 present on the TEBA0841 board to configure options and set parameters. The following table describes the of the particular switches:

Table 12: DIP-switch S1, see also 4x5 Module Controller IOs

VCCIO Selection Jumper

On the TEBA0841 carrier board different VCCIO configurations can be selected by the jumper header J26, J27, J5 and J6.

TE 4 x 5 Modules have a standard assignment of PL-bank I/O voltages on the B2B connectors, which will be fed with I/O voltage from base-board.

Table 13: Base-board PL-bank I/O voltages VCCIOA ... VCCIOD

Following table describes how to configure the base-board supply-voltages by jumpers:

Table 14: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2' means pins 1 and 2 are connected, 'Jx: 3-4' means pins 3 and 4 are connected, and so on

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of the carrier board depends mainly on the mounted SoM's FPGA design running on the Zynq device.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 15: Typical power consumption

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended.

Power Supply

Power supply with minimum current capability of 3A at 3.3V for system startup is recommended.

The on-board voltages of the carrier board will be powered up with an external power-supply with nominal voltage of 3.3V.

The external power-supply can be connected to the board by the following pins:

Table 16: Connector pins capable for external 3.3V power supply

Power Distribution Dependencies

The PL-bank I/O voltages 1.8V, 2.5V and 3.3V will be available after the mounted SoM's 3.3V voltage level has reached stable state on B2B-connector pins JM2-10 and JM2-12 (JB2-9, JB2-11), meaning that all on-module voltages have become stable and module is properly powered up.

Following diagram shows the distribution of the external input voltage of nominal 3.3V to the components:

Power Rails

The voltage direction of the power rails is from board and on-board connectors' view:

Table 17: Power pin description of B2B module connector

Table 18: Power Pin description of on-board connector

Table 19: Power Pin description of VCCIO selection jumper pin header

Table 20: Power pin description of peripheral connector

Table 21: Power pin description of XMOD/JTAG connector

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings

Table 22: Board absolute maximum ratings

Recommended Operating Conditions

Table 23: Module recommended operating conditions

Operating Temperature Ranges

TEBA0841 carrier board operating temperature range is industrial grade: -40°C to +85°C.

Please check the operating temperature range of the mounted SoM, which determine the relevant operating temperature range of the overall system.

Physical Dimensions

Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). This is because of the 100mil pin headers used, see also explanation below. To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.

• Module size: 56mm × 75mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 8mm.

• PCB thickness: 1.65mm.

• Highest part on the PCB is the SFP+ connector, which has an approximately 11.3mm overall hight. Please download the step model for exact numbers.

Revision History

Hardware Revision History

Table 24: Module hardware revision history

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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Table 24: Document change history

...

Download PDF Version of this Document.

Overview

Refer to https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/carrier_boards/TEBA0841 for downloadable version of this manual and additional technical documentation of the product.

The Trenz Electronic TE0705 Carrier Board is a base-board for 4x5 SoMs, which exposes the MIO- and the PS/PL-pins of the SoM to accessible connectors and provides a whole range of on-board components to test and evaluate Trenz Electronic 4x5 SoMs.

See page "4 x 5 cm carriers" to get information about the SoMs supported by the TE0705 Carrier Board.

Block Diagram

Figure 1: TE0705-04 Block Diagram

Main Components

Figure 2: 4x5 SoM carrier board TE0705-04

TE0705-04:

1. ARM JTAG Connector (DS-5 D-Stream) J15 - PJTAG to EMIO multiplexing needed
2. 12-pin IDC header socket J1 (right angle, max. VCCIO-voltage: 3.3V): mapped to 8 Zynq PS MIO0-bank-pins (MIO0, MIO9 to MIO15), 6 pins (MIO10 to MIO15) are additionally connected to TE0705 System-Controller-CPLD

3. RJ45 GbE Connector

4. SD Card Socket - Zynq SDIO0 Bootable SD port
5. 12-pin IDC header socket (right angle) J2 for access to Zynq-module's PL IO-bank pins (not usable as LVDS-pairs, only single-ended IOs, max. VCCIO-voltage: VIOTB)
6. Micro USB Connector J12 (Device, Host or OTG Modes)
7. Battery holder for CR1220 (RTC backup voltage)
8. 12-pin IDC header socket (vertical) J5 for access to Zynq-module's PL IO-bank pins (4 LVDS-pairs, max. VCCIO-voltage: VIOTB)
9. 12-pin IDC header socket (vertical) J6 for access to Zynq-module's PL IO-bank pins (4 LVDS-pairs, max. VCCIO-voltage: VIOTB)
10. User Push-Button S2 ("RESTART" button by default)
11. User Push-Button S1 ("RESET" button by default)
12. User LEDs D6, D7, D8, D9 (function mapping depends on firmware of System-Controller-CPLD)
13. User LEDs D4, D5, D14, D15 (same as above)
14. Mini USB Connector (USB JTAG and UART Interface) J7
15. User 4-bit DIP-Switch S3
16. User 4-bit DIP-Switch S4
17. FTDI FT2232HQ USB 2.0 High Speed to UART/FIFO
18. Lattice Semiconductor MachXO2 1200HC System-Controller-CPLD
19. Jumper J4 to fix user button S2 to switched state
20. 40-Pin-Header J13 for access to PL IO-bank-pins
21. 40-Pin-Header J11 for access to PL IO-bank-pins
22. Samtec Razor Beam™ high-speed hermaphroditic 50 positions terminal strip, board to board connector, JB1
23. Samtec Razor Beam™ high-speed hermaphroditic 50 positions terminal strip, board to board connector, JB2
24. Samtec Razor Beam™ high-speed hermaphroditic 50 positions terminal strip, board to board connector, JB3
25. Barrel jack for 12V Power Supply J10
26. Jumper J21 to select supply voltage VIOTB
27. Jumper J9, J19, J20 to select supply voltage USB-VBUS

Key Features

• Overvoltage-, undervoltage- and reversed- supply-voltage-protection
• Barrel jack for 12V power supply
• Carrier Board System-Controller-CPLD Lattice MachXO2 1200HC, programable by Mini-USB JTAG-Interface J7
• Zynq-module programable by ARM-JTAG-Interface-Connector (J15) or by System-Controller-CPLD via Mini-USB JTAG-Interface J7
• RJ45 Gigabit Ethernet MagJack with 2 integrated LEDs
• 2x 40-Pin-Header J11 and J13  for access to Zynq-module's PL IO-bank-pins, operable with fixed (3.3V) or adjustable IO-voltage VIOTB (not usable as LVDS-pairs, only single-ended IOs)
  
• USB JTAG- and UART-Interface (FTDI FT2232HQ) with Mini-USB-Connector J7
  
• 8 x user LEDs routed to System-Controller-CPLD, 8 x red
• 2 x user-push button routed to System-Controller-CPLD; by default configured as system "RESET" and "RESTART" button (depends on CPLD-Firmware)
  
• 2 x 4-bit DIP-Switch for base-board-configuration (3 switches routed to System-Controller-CPLD, 3 switches to set voltage FMC_VADJ, 1 switch routed to Zynq-module (MIO0), 1 switch enables Mini-USB JTAG-Interface J7)
  
• 12-pin IDC header socket (vertical) J5, J6 for access to Zynq-module's LVDS-pairs (max. VCCIO-voltage: VIOTB)
• 12-pin IDC header socket (right angle) J1 for access to Zynq-module's MIO0-bank-pins MIO0, MIO9 ... MIO15 (J1-6 (MIO12) buffered by Schmitt-Trigger-Buffer (5.0V Hysteresis), else max. VCCIO-voltage 3.3V)
• 12-pin IDC header socket (right angle) J2 for access to Zynq-module's PL IO-bank-pins (max. VCCIO-voltage: VIOTB)
  
• Micro SD card socket, can be used to boot system
• Micro-USB-Interface (J12) connected to Zynq-module (Device, Host or OTG modes)
• Trenz 4x5 module Socket (3 x Samtec LSHM series connectors)

Interfaces and Pins

Micro SD Card Socket

Micro SD Card socket is not directly wired to the B2B connector pins, but through a Texas Instruments TXS02612 SDIO Port Expander, which is needed for voltage translation due to different voltage levels of the Micro SD Card and MIO-bank of the Xilinx Zynq-module. The Micro SD Card has 3.3V signal voltage level, but the MIO-bank on the Xilinx Zynq-module has VCCIO 1.8V.

Dual channel USB to UART/FIFO

The TE0705 Carrier Board has on-board USB 2.0 High Speed to UART/FIFO IC FT2232HQ from FTDI. Channel A can be used as JTAG-Interface (MPSSE) to program the System-Controller-CPLD, Channel B can be used as UART-Interface routed to CPLD. There are also 6 additionally bus-lanes available for user-specific use. The FT2232HQ-Chip can also be used as FIFO in FT245 asynchronous mode.

There is also a standard 256 Byte EEPROM connected to the FT2232HQ-chip available to store custom configuration settings. EEPROM settings can be changed using FTDI provided tools that can be downloaded from FTDI website. See FTDI website for more information.

USB Interface

The TE0705 carrier board has two physical USB-connectors:

• J7 as mini-USB-connector wired to on-board FTDI FT2232HQ chip.
• J12 as micro-USB-connector wired to B2B connector JB3 (there is usually an USB-transceiver on the SoMs).

JTAG Interface

JTAG access to the CPLD and Xilinx Zynq-module is provided via Mini-USB JTAG Interface J7 (FTDI FT2232H) and controlled by DIP switch S3-3.

The JTAG port of the CPLD is enabled by setting switch S3-3 labeled as "ENJTAG" to the OFF-position.

LEDs

There are eight LEDs (D6, D7, D8, D9, D4, D5, D14, D15) available to the user. All LEDs are red colored and connected to the on-board System-Controller-CPLD. Their functions are programmable and depend on the firmware of the System-Controller-CPLD. For detailed information, please refer to the documentation of the TE0705 System-Controller-CPLD.

One green LED D22 shows the availability of the 3.3V supply voltage of the TE0701 Carrier Board.

4-bit DIP-switch S3

On the TE0705 Carrier Board there is a 4-bit DIP-switch S3 (see (15) in Figure 1) available. The default switch mapping is as follows:

...

4-bit DIP-switch S4

Additionally, on the TE0705 Carrier Board there is a 4-bit DIP-switch S3 (see (16) in Figure 1) available. The signals of the switch are routed to carrier board's System-Controller-CPLD and are fully user-configurable depending on a customer developed CPLD-firmware. Please refer to the documentation of the TE0705 System-Controller-CPLD to get information how to put these user-switches in operation.

User-Push-Buttons

On the TE0705 Carrier Board there are two push buttons (S1 and S2) and are routed to the System-Controller-CPLD and available to the user. The default mapping of the push buttons is as follows:

...

The functionality of the push buttons depends on the CPLD-firmware. For detailed information of the function of the push buttons, please refer to the documentation of the TE0705 System-Controller-CPLD.

Ethernet

The TE0701 Carrier Board has a RJ45 Gigabit Ethernet MagJack (J14) with two LEDs.

On-board Ethernet MagJack J14 pins are routed to B2B connector JB1 via MDI. The center tap of the Magnetics is not connected to module's B2B connector.

PHY LEDs are not connected directly to the module's B2B connectors as the 4x5 module have no dedicated PHY LED pins assigned. PHY LEDs are connected to the TE0705 System-Controller-CPLD, that can route those LEDs to some module's I/O Pins. In that case the CPLD has to map the PHY LEDs to corresponding pins.

See documentation of the TE0705 System-Controller-CPLD to get information of the function of the PHY LEDs.

IDC header sockets J5 and J6

J5 and J6 sockets signal routing is done as differential pairs for pins 1-3, 2-4, 5-7, 6-8. The differential pairs are operable with VCCIO-voltage VIOTB.

Please use Master Pinout Table table as primary reference for the pin mapping information.

IDC header socket J1

Zynq-module's MIO0-bank pins MIO0, MIO9-MIO15 are accessible on socket J1. Maximal VCCIO-voltage is 3.3V on this socket. An exception here is the MIO12-pin, which is buffered with a Schmitt-Trigger-Buffer with a Hystersis of 5.0V.

IDC header socket J2

Zynq-module's PL IO-bank pins are accessible on socket J2. The IO-signals are routed from this socket to B2B-connector JB3 and are only single-ended IOs, hence this signal-pins are not usable as differential pairs. Maximal VCCIO-voltage is VIOTB on this socket.

40-pin headers J11 and J13

40-Pin-Header J11 and J13  for access to Zynq-module's PL IO-bank-pins on B2B-connectors JB1 and JB2. Operable with fixed (3.3V) or adjustable VCCIO-voltage VIOTB (not usable as LVDS-pairs, only single-ended IOs).

Power

Power Supply

Power supply with minimum current capability of 3A at 12V for system startup is recommended.

Power-On Sequence

The on-board voltages of the carrier board will be powered up simultaneously after one single power-supply with a nominal voltage of 12V is connected to the power-jack J10.

The PL IO-bank supply voltage FMC_VADJ will be available after the output of the 5.0V-DCDC-converter is active and the pin EN_FMC of the SC-CPLD is asserted.

Figure 3: Power-Up sequence diagram

Configuring VCCIO 

On the TE0705 carrier board different VCCIO configurations can be chosen by jumper J21 and DIP-switch S3.

The purpose of the jumper and the DIP-switch S3 of the Carrier Board will be explained in the following sections.

Select VCCIO-voltage by DIP-Switch S3

There is the possibility to select the module's PL IO-bank's supply voltage VIOTB to fixed adjustable voltages VADJ. Therefore, the jumper J21 has to be set to the position 1, 2-3, to connect the pins 'VIOTB' and 'ADJ'. On position 1-2, 3, the supply voltage VIOTB will be fixed to 3.3V

Table 3 shows the switch-configuration of the DIP-switch S3 to set the voltage VADJ.

Note: The configuration of VADJ depends on the used firmware of the System-Controller-CPLD. For detailed information, refer to the documentation of the TE0705 System-Controller-CPLD.

...

S3-1 (CM1)

...

S3-2 (CM2)

...

VADJ Value

...

OFF

...

OFF

...

1.8V

...

OFF

...

ON

...

2.5V

...

ON

...

OFF

...

3.3V

...

ON

...

ON

...

1.8V (Note: Also Zynq-module's SC-CPLD JTAG-access is enabled, see section JTAG in the documentation of the TE0705 System-Controller-CPLD.)

Table 3: Switch S3 positions for fixed values of the VADJ voltage

Configuring Power Supply of the Micro USB Connector (Device, Host or OTG Modes) 

The TE0705 carrier board can be configured as a USB host. Hence, it must provide from 5.25V to 4.75V to the board side of the downstream connection (micro USB port on J12). To provide sufficient power, a TPS2051 power distribution switch is located on the carrier board in between the 5V power supply and the Vbus signal of the USB downstream port interface. If the output load exceeds the current-limit threshold, the TPS2051 limits the output current and pulls the overcurrent logic output (OC_n) low, which is routed to the on-board CPLD. The TPS2051 is put into operation by setting J19 CLOSED. J20 provides an extra 100µF decoupling capacitor (in addition to 10µF) to further stabilize the output signal. Moreover, a series terminating resistor of either 1K (J9: 1-2, 3) or 10K (J9: 1, 2-3) is selectable on the "USB-VBUS" signal. Both signals, USB-VBUS and VBUS_V_EN (that enables the TPS2051 on "high") are routed (as well as the corresponding D+/- data lines) via the on-board connector directly to the USB 2.0 high-speed transceiver PHY on the mounted SoM, which is, in turn, connected to the Zynq FPGA. In summary, the default jumper settings are the following: J9: 1-2, 3 (1K series terminating resistor); J19: CLOSED (TPS2051 in operation); J20: CLOSED (100 µF added).

Additionally, the TE0705 carrier board is equipped with a second mini USB port J7 that is connected to a "USB to multi-purpose UART/FIFO IC" from FTDI (FT2232HQ) and provides a USB-to-JTAG interface between a host PC and the TE0705 carrier board and the Zynq-module, respectively. Because it acts as a USB function device, no power switch is required (and only a ESD protection must be provided) in this case.

Summary of VCCIO-configuration

On the TE0705 carrier board all PL IO-bank's supply voltages of the 4x5 SoM (VCCIOA, VCCIOB, VCCIOC, VCCIOD; see 4x5 Module Integration Guide) are connected to the VCCIO-voltage VIOTB, which is either fixed to 3.3V (J21: 1-2, 3) or selectable with the adjustable supply-voltage VADJ (J21: 1, 2-3). The supply-voltages have following pin assignments on B2B-connectors:

...

base-board

supply-voltages

...

base-board voltages and signals connected with

...

JB1-10, JB1-12,

JB2-2, JB2-4, JB2-6,

JB2-8, JB2-10

...

VCCIOA (JM1-9, JM1-11),

VCCIOB (JM2-1, JM2-3), VCCIOC (JM2-5),

VCCIOD (JM2-7, JM2-9)

...

VCCIO3 (Systm-Controller-CPLD pin 5, 11, 23),

J15 VTREF,

J11, J13, J2, J5 and J6 VCCIO

Table 4: base-board supply-voltage VIOTB

...

base-board supply-voltages vs voltage-levels

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(J20: 1-2: additional decoupling-capacitor 100 µF)

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Table 5: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2, 3' means pins 1 and 2 are connected, 3 is open. 'Jx: 1, 2-3' means pins 2 and 3 are connected, 1 is open

Power On Reset (POR)

On the TE0705 the 5.0V and 3.3V power supply rails are generated by high performance DC-DC-converters from the external 12V supply. While the 3.3V plane supplies several on-board components (e.g., Lattice CPLD and FTDI Dual USB UART/FIFO IC), the 5V plane is mainly provided to power supply of the module to be carried (e.g., TE0720 Zynq SoC module). For the latter, however, special considerations must be taken (see TE0720 Power Supply). Therefore, the on-module system controller (SC) must be provided with information about the power-on-reset (POR) process, namely, the following control signals EN1, RESIN, and NOSEQ. And the SC provides, in turn, the status signal PGOOD down to the on-board System-Controller-CPLD.

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Table 6: Generation of PGOOD-signal

Technical Specifications

Absolute Maximum Ratings

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Vin supply voltage

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11.4

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V

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Storage Temperature

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°C

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Recommended Operating Conditions

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Physical Dimensions

• Board size:  PCB 170.4 mm ×  98 mm. Notice that some parts the are hanging slightly over the edge of the PCB like the mini USB-jacks (ca. 1.4 mm) and the Ethernet RJ-45 jack (ca 2.2 mm), which determine the total physical dimensions of the carrier board. Please download the assembly diagram for exact numbers.

• Mating height of the module with standard connectors: 8mm

• PCB thickness: ca. 1.65mm

• Highest part on the PCB is the Ethernet RJ-45 jack, which has an approximately 17 mm overall hight. Please download the step model for exact numbers.

 All dimensions are given in mm.

Figure 4: Physical Dimensions of the TE0705-04 carrier board

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Board operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

ca. 110 g - Plain board

Document Change History

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0.1

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Initial document

Hardware Revision History

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Notes

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Figure 5: Hardware revision Number

Hardware revision number is printed on the PCB board next to the model number separated by the dash.

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