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JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on B2B. In the carrier board TEB0835 can be activated this pin with S1-4 dip switch.
| CPLD_JTAGEN (B2B J1-30) | S1-4 on TEB0835 Carrier Board | Description |
|---|---|---|
| 0 | OFF | FPGA access |
| 1 | ON | CPLD access |
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If the FPGA correctly programmed (DONE signal is high) and the power-on sequencing state is RDY then the User IOs can be shown in the following table:
| Function | DesignatorInterfacePin Name | Schematic | FPGA Pin | NumberBoard | Note | Interface | Connected in the Hardware with | Designator | Pin Name | Pin Number | Board | after programming the FPGA connected with | Designator | Pin Name | Pin Number | Board | ||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dip Switch | S1-3 | CPLD_IO2 | --- | TEB0835 | B2B | CPLD | U31 | CPLD_IO2 | 40 | TE0835 | FPGA | U1 | FPGA_IO1 | AE16 | TE0835 | |||||
| USER signal | B2B (J1-32) | FPGA_IO1 | AE16 | source by TEB0835 Dip Switch S1-3, in case FPGA is programmed | ||||||||||||||||
| LED (D1) | -- | FPGA_IO0 | AE18 | controls LED, in case FPGA is programmed | FPGA | U1 | FPGA_IO0 | AE18 | TE0835 | --- | CPLD | U31 | FPGA_IO0 | 27 | TE0835 | LED | D1 | --- | --- | TE0835
Boot Mode
Boot Modes can be selected via B2B Pin Mode.
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Overview
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