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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via Vitis.
Refer to http://trenz.org/te0813-info for the current online version of this manual and other available documentation.
Key Features
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Revision History
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Example
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Overview
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Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via Vitis.
Refer to http://trenz.org/te0813-info for the current online version of this manual and other available documentation.
Key Features
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Revision History
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Date
Vivado
Project Built
Authors
Description
TE0813-test_board-vivado_2020.2-build_9_20211116073013.zip
- new variants
TE0813-test_board_noprebuilt-vivado_2020.2-build_8_20211028144418.zip
- initial release
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| Known Issues
| Workaround | To be fixed version | QSPI Flash | Programming QSPI flash fails sometimes | use Vivado 2019.2 for programming |
Requirements
Software
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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title | Hardware Modules |
*used as reference
Note: Design contains also Board Part Files for TE0813+TEBF0818 configuration, this board part files are not used for this reference design.
Design supports following carriers:
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title | Hardware Carrier |
Carrier Model
Notes
TEBF0818*
Used as reference carrier.
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Release Notes and Know Issues
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Requirements
Software
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*used as reference
Additional HW Requirements:
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Hardware
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For general structure and usage of the reference design, see Project Delivery - Xilinx devices
Design Sources
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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| Design sources
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Vivado | <project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files | Vivado Project will be generated by TE Scripts | ||||||||||||||||||||||||||||||
Vitis | <project folder>\sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
Additional Sources
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Type
Location
Notes
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Prebuilt
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Notes :
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File
File-Extension
Description
Distro Boot file
Debian SD-Image
*.img
Debian Image for SD-Card
MCS-File
*.mcs
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File
*.mmi
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
SREC-File
*.srec
Converted Software Application for MicroBlaze Processor Systems
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Design supports following carriers:
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*used as reference |
Additional HW Requirements:
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*used as reference |
Content
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For general structure and usage of the reference design, see Project Delivery - AMD devices
Design Sources
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Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- AMD Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths--------------
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title | Prebuilt files (only on ZIP with prebult content) |
File
File-Extension
Description
BIF-File
*.bif
File with description to generate Bin-File
BIN-File
*.bin
Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File
*.bit
FPGA (PL Part) Configuration File
Diverse Reports
---
Report files in different formats
LabTools Project-File
*.lpr
Vivado Labtools Project File
Software-Application-File
*.elf
Software Application for Zynq or MicroBlaze Processor Systems
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths----------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
Important: Use Board Part Files, which did not ends with *_tebf0818
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") TE::hw_build_design -export_prebuilt
Info Using Vivado GUI is the same, except file export to prebuilt folder.
Generate Programming Files with Vitis
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
Launch
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Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp hello_te0813
Note To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup
SD-Boot mode
This does not work, because SD controller is not selected on PS.
JTAG
Load configuration and Application with Vitis Debugger into device
Usage
QSPI Boot:
Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Select QSPI as Boot Mode
Info Note: See TRM of the Carrier, which is used.
Power On PCB
Expand title boot process 1. ZynqMP Boot ROM loads FSBL from QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from QSPI into DDR,
System Design - Vivado
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PS Interfaces
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Activated interfaces:
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
Not needed.
Software Design - Vitis
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For Vitis project creation, follow instructions from:
Application
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---------------------------------------------------------- FPGA Example ----------------------------------------------------------FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 20202023.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 20202023.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: ---------------------------------------------------------- Zynq Example: fsblTE modified 20202023.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2020.2 FSBL General:
---------------------------------------------------------- ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 20202023.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2020.2 FSBL General:
zynqmp_pmufw
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example:Xilinx default PMU firmware. ----------------------------------------------------------General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
zynqmp_fsbl
TE modified 20202023.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
zynqmp_fsbl_flash
TE modified 2020.2 FSBL
GeneralModule Specific:
- Modified Add Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.call TE Files start with te_*
- Si5338 Configuration
- OTG+PCIe Reset over MIO
- I2C MUX for EEPROM MAC
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0813
Hello TE0813 is a Xilinx Hello World example as endless loop instead of one console output.
Additional Software
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No additional software is needed.
Appx. A: Change History and Legal Notices
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Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
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repeatTableHeaders | default | style | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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infoType | Modified by | type | Flat
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2021-10-28 | v.2 | Manuela Strücker |
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