Overview
Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via Vitis.
Refer to http://trenz.org/te0813-info for the current online version of this manual and other available documentation.
Key Features
Vitis/Vivado 2023.2
QSPI
Custom Carrier (minimum PS Design with available module components only)
Modified FSBL (some additional outputs only)
Revision History
Release Notes and Know Issues
| Issues | Description | Workaround | To be fixed version |
|---|---|---|---|
| Xilinx Software | Incompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Request | use corresponding board files for the Vivado versions | -- |
| QSPI Flash | Programming QSPI flash fails sometimes | use Vivado 2019.2 for programming |
Known Issues
Requirements
Software
| Software | Version | Note |
|---|---|---|
| Vitis | 2023.2 | needed, Vivado is included into Vitis installation |
Software
Hardware
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
Note: Design contains also Board Part Files for TE0813+TEBF0818 configuration, this board part files are not used for this reference design.Design supports following carriers:
Carrier Model | Notes |
|---|---|
TEBF0818* | Used as reference carrier. |
*used as reference
Hardware Carrier
Additional HW Requirements:
Additional Hardware | Notes |
|---|---|
--- | --- |
*used as reference
Additional Hardware
Content
For general structure and usage of the reference design, see Project Delivery - AMD devices
Design Sources
| Type | Location | Notes |
|---|---|---|
| Vivado | <project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files | Vivado Project will be generated by TE Scripts |
| Vitis | <project folder>\sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
Design sources
Additional Sources
Type | Location | Notes |
|---|---|---|
--- | --- | --- |
Additional design sources
Prebuilt
File | File-Extension | Description |
|---|---|---|
BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Prebuilt files (only on ZIP with prebult content)
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- AMD Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
_create_win_setup.cmd/_create_linux_setup.sh------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
Press 0 and enter to start "Module Selection Guide"
- Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow
Important: Use Board Part Files, which did not ends with *_tebf0818
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")TE::hw_build_design -export_prebuilt
Using Vivado GUI is the same, except file export to prebuilt folder.
Generate Programming Files with Vitis
run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
Launch
Programming
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
run on Vivado TCL (Script programs BOOT.bin on QSPI flash)TE::pr_program_flash -swapp hello_te0813
To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup
SD-Boot mode
This does not work, because SD controller is not selected on PS.
JTAG
Load configuration and Application with Vitis Debugger into device
Usage
QSPI Boot:
Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Select QSPI as Boot Mode
Note: See TRM of the Carrier, which is used.
Power On PCB
System Design - Vivado
Block Design
Block Design
PS Interfaces
Activated interfaces:
Type | Note |
|---|---|
DDR | |
QSPI | MIO |
UART0 | MIO, please select other one, if you have connected UART to second controller or other MIO |
SWDT0..1 | |
TTC0..3 |
PS Interfaces
Constrains
Basic module constrains
_i_bitgen.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]
Design specific constrain
Not needed.
Software Design - Vitis
For Vitis project creation, follow instructions from:
Application
Template location: "<project folder>\sw_lib\sw_apps\"zynqmp_fsbl
TE modified 2023.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- OTG+PCIe Reset over MIO
- I2C MUX for EEPROM MAC
hello_te0813
Hello TE0813 is a Xilinx Hello World example as endless loop instead of one console output.
Additional Software
No additional software is needed.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
Date | Document Revision | Authors | Description |
|---|---|---|---|
| |||
2023-09-27 | v.12 | Manuela Strücker |
|
2023-08-14 | v.11 | Manuela Strücker |
|
2022-10-20 | v.6 | Manuela Strücker |
|
| 2022-09-06 | v5 | Manuela Strücker |
|
| 2021-10-28 | v.2 | Manuela Strücker |
|
All |
Document change history.
Legal Notices
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Document Warranty
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Copyright Notice
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Technology Licenses
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
Environmental Protection
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REACH, RoHS and WEEE
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WEEE
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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
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