Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via Vitis.
Refer to http://trenz.org/te0813-info for the current online version of this manual and other available documentation.
Custom Carrier (minimum PS Design with available module components only)
Modified FSBL (some additional outputs only)
Special FSBL for QSPI Programming
Release Notes and Know Issues
|Issues||Description||Workaround||To be fixed version|
|Xilinx Software||Incompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Request||use corresponding board files for the Vivado versions||--|
|QSPI Flash||Programming QSPI flash fails sometimes||use Vivado 2019.2 for programming|
|Vitis||2021.2.1||needed, Vivado is included into Vitis installation|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
|Module Model||Board Part Short Name||PCB Revision Support||DDR||QSPI Flash||EMMC||Others||Notes|
*used as reference
Note: Design contains also Board Part Files for TE0813+TEBF0818 configuration, this board part files are not used for this reference design.
Design supports following carriers:
Used as reference carrier.
*used as reference
Additional HW Requirements:
*used as reference
For general structure and usage of the reference design, see Project Delivery - Xilinx devices
|Vivado Project will be generated by TE Scripts|
|Vitis||<project folder>\sw_lib||Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation|
File with description to generate Bin-File
Flash Configuration File with Boot-Image (Zynq-FPGAs)
FPGA (PL Part) Configuration File
Report files in different formats
|Hardware-Platform-Description-File||*.xsa||Exported Vivado hardware description file for Vitis and PetaLinux|
Vivado Labtools Project File
Software Application for Zynq or MicroBlaze Processor Systems
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
- Xilinx Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Press 0 and enter to start "Module Selection Guide"
- Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow
Important: Use Board Part Files, which did not ends with *_tebf0818
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Using Vivado GUI is the same, except file export to prebuilt folder.
Generate Programming Files with Vitis
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup
This does not work, because SD controller is not selected on PS.
Load configuration and Application with Vitis Debugger into device
Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Select QSPI as Boot Mode
Note: See TRM of the Carrier, which is used.
Power On PCBboot process
1. ZynqMP Boot ROM loads FSBL from QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from QSPI into DDR,
System Design - Vivado
MIO, please select other one, if you have connected UART to second controller or other MIO
Basic module constrains
Design specific constrain
Software Design - Vitis
For Vitis project creation, follow instructions from:
Template location: "<project folder>\sw_lib\sw_apps\"
TE modified 2021.2 FSBL
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- OTG+PCIe Reset over MIO
- I2C MUX for EEPROM MAC
TE modified 2021.2 FSBL
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
Hello TE0813 is a Xilinx Hello World example as endless loop instead of one console output.
No additional software is needed.
Appx. A: Change History and Legal Notices
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