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Table of Contents

Table of Contents

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Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Image RemovedImage Added

Figure 1: TEB0729-02 03 block diagram.

Main Components

 

Figure 2: TEB0729-02 03 main components (picture shows PCB REV02).

  1. 5V barrel jack, J12
  2. RJ-45 Gigabit Ethernet MegJack, J3
  3. RJ-45 10/100-BaseT Ethernet MegJack, J4
  4. RJ-45 10/100-BaseT Ethernet MegJack, J5
  5. VG96 connector placeholder, J9
  6. XMOD (TE0790) header, JB3
  7. 2-pin header for VBAT-IN supply-voltage, J2
  8. 2x6 pin header for setting VCCIO_33, J6
  9. 2x6 pin header for setting VCCIO_13, J7
  10. MicroSD Card socket, J1
  11. Red LED, D1
  12. Push Button, S1
  13. Micro USB2.0 B Receptacle (optional USB2.0 Type A socket)
  14. VG96 connector placeholder, J8
  15. B2B Connector, JB1
  16. B2B Connector, JB2
  17. 4-bit DIP-switch, S2

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The TEB0729 Carrier Board's Board-to-Board Connectors (B2B) have the same pin-assignment as the mounted Zynq SoM due to its hermaphroditic structure. By this connectors, the MIO- and PL-IO-bank's pins and further interfaces of the Zynq SoM can be accessed. A large quantity of these I/O's are also usable as  as LVDS-pairs. The connectors provide also VCCIO voltages to operate the I/O's properly.

Following table gives a summary of the available I/O's, interfaces and LVDS-pairs of the B2B connectors JB1 and JB2:

VG96 B2B Connector DesignatorInterfacesCount of IO'sCount of LVDS-pairsAvailable VCCIO'sInterfacesNotes
JB172481.8V, 2.5VUser IO24 single ended-
48 single ended or 24 differential--
JB2

User IO

54 single ended-
10 single ended or 5 differential-
I²C2-
SD IO7-
UART2-
USB2.06-645VCCIO_13, VCCIO_33
3.3V		I²C,
SD IO,
UART,
USB2.0,
2x 10/100-BaseT Ethernet,12-
GbE MDI and SGMII,14-
JTAG

The 5 LVDS-pairs on connector JB2 have
the prefix 'DISP' in the schematic net names.

The I²C, SD IO and the UART interface pins are connected
to MIO-pins of the mounted Zynq-SoM, so this pins can also be
used for user and general purposes.

Table 2: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

4-

Table 2: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

VG96 VG96 Connector

The TEB0729 Carrier Board has soldering pads provides as place-holders to mount VG96 connectors J8 and J9 to get access the PL-IO-bank's pins and further interfaces of the Zynq SoM. With mounted VG96 connectors, SoM's IO's are available to the user, a large quantity of these I/O's are also usable as  LVDS-pairs.

On the VG96 connector J9 are signals assigned to control the SoM and the interfaces of the SoM's Zynq chip device and of its on-module peripherals:

Following table gives a summary of the pin-assignment, available interfaces and functional IO's of the VG96 connectors J8 and J9:

I²C
GbE SGMII
VG96 ConnectorControl Signals and InterfacesCount of IO'sCount of LVDS-pairsInterfacesSoM Control SignalsNotes
J87248---
Notes
J8User IO24 single ended-
48 single ended or 24 differential-
J9

User IO

54 single ended-
10 single ended or 5 differential-J9645
'NRST_IN' , (pin J9-A29Drive to ground (Push Button S1, JB3-11 (G) on XMOD header) to reset the SoM. 1)'NRST_OUT', ), 'RST_STATUS' (pin J9-B30Incoming reset signal from SoM's watchdog (implemented on SoM's SC CPLD). 1))2

These pins are dedicated to the specific Reset-functionality of the TE0729 SoM.

'BOARD_STAT' , (pin J9-B32)1-Frequently flipping signal indicating running SoM. Routed also to XMOD Header, pin JB3-9 (E).
'BOOT_MODE1' , (pin J9-C31Bootmode pin 1, use in conjunction with Bootmode pin 2.), 'BOOT_MODE2' , (pin J9-C32)Bootmode pin 2, use in conjunction with Bootmode pin 1.2Binary bootmode code of SoM, also connected to DIP S2
I²C2I²C1 interface of module
GbE SGMII4SGMII interface of on-module GbE PHY

Table 3: General overview of PL I/O signals, SoM's interfaces and control signals  connected to the VG96 connectors.

HW-modification Concerning Reset-Signals

1) The pins with the schematic net names 'NRST_IN' (JB2-89) and 'NRST_OUT' (JB2-91) are swapped as part of a HW-modification to rework the Reset-signals of the Carrier-Board in conjunction with the TE0729 SoM.

Refer to the SC CPLD documentation, section "Watchdog" to get further detailed information about the Reset-functionality of the Carrier Board and SoM before and after the HW-modification and the required SC CPLD firmware revision of the TE0729 SoM for each version of the SoM.

JTAG Interface

JTAG Interface

JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JB3. With the TE0790 XMOD USB2.0 to JTAG adapter, the Zynq device on the mounted SoM JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JB3. With the TE0790 XMOD USB2.0 to JTAG adapter, the Zynq chip on the mounted SoM can be programed via USB2.0 interface.

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The SD IO interface of the SoM's Zynq chip device (MIO-bank) is routed to the on-board MicroSD Card socket J1. By this interface, the Zynq chip device can be booted from an inserted MicroSD Card:

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The TEB0729 Carrier Board is equipped with a Micro USB2.0 B (receptacle) socket J11 with board-revision TEB0729-0203B, USB2.0 Type A socket is fitted on board-revision TEB0729-0203A.

The differential data signals of the USB2.0 socket are routed to the B2B connector JB2, where they can be accessed by the USB2.0 transceiver of the mounted SoM. The USB2.0 connector can be used for Device mode, OTG Mode or Host Modes. For USB Host mode, the Carrier Board is additionally equipped with a power distribution switch U3 to provide the USB2.0 interface with the USB supply voltage USB-VBUS with nominal value of 5V. OTG mode is not available with USB2.0 Type A socket.

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10/100-BaseT PHY Signal Schematic NameB2BConnected toNotes
ETH1_RX_P

JB2-26

J4-3 -
ETH1_RX_NJB2-28J4-6-
ETH1_TX_PJB2-20J4-1-
ETH1_TX_NJB2-22J4-2-
ETH1_CTREFJB2-30J4-4, J4-5Centre Tap Reference pointETH1_LED0JB2-34Yellow MegJack J4 LED-
ETH1_LED1JB2-32Green MegJack J4 LED-




ETH2_RX_PJB2-8J5-3-
ETH2_RX_NJB2-10J5-6-
ETH2_TX_PJB2-2J5-1-
ETH2_TX_NJB2-4J5-2-
ETH2_CTREFJB2-18J5-4, J5-5Centre Tap Reference pointETH2_LED0JB2-16Yellow MegJack J5 LED-
ETH2_LED1JB2-14Green MegJack J5 LED-

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JB3 pinSignal Schematic Net NameB2BNote
C (pin 4)TCKJB2-119 -
D (pin 8)TDOJB2-117 -
F (pin 10)TDIJB2-115 -
H (pin 12)TMSJB2-113 -
A (pin 3)USART0_TXJB2-96 -
B (pin 7)USART0_RXJB2-94 -
E (pin 9)BOARD_STATJB2-112also connected to VG96 connector pin J9-B32
G (pin 11) 2)NRST_INJB2-89

also connected to VG96 connector pin J9-A29

Table 12: XMOD header signals and connections.  2) Pin connected to push button S1 on XMOD FTDI JTAG Adapter

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the Carrier Board. Set the DIP-switch with the setting:

...

Table 13: XMOD adapter board DIP-switch positions for voltage configuration.

On-board Peripherals


Note

Use Xilinx compatible TE0790 adapter board (designation TE0790-xx with out 'L') to program the Zynq device.

The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download.

On-board Peripherals

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DIP-switches S2Signal Schematic Net NameFunctionNote
S2-1JTAGSEL

Select Zynq chip device or SC CPLD programming of mounted SoM:

OFF:  Zynq chip programming.device in JTAG chain
ON:    SC CPLD programmingin JTAG chain

Refer also to the TE0729 SC CPLD documentation for detailed information about JTAG update.
S2-2BOOT_MODE1Select first bit of boot mode codeRefer to TE0729 TRM and SC CPLD documentation for detailed information about boot modes.
S2-3BOOT_MODE2Select second bit boot mode code
S2-4xxnot used

Table 14: DIP-Switch S2 SoM configuration settings.

TE0729 Bootmodes

If TE0729 is mounted, following bootmodes can be configured by setting the DIP-switches S2-2 and S2-3:


Boot Boot ModeS2-2S2-3
JTAGONON
SDOFFOFF
QSPIONOFF

Table 15: Bootmode  Boot Modes configuration via DIP-switch S2 .

The selected bootmode via DIP-switch S2 depends also on the current configured SC CPLD firmware on the mounted SoM and may vary.

...

with default TE0729 CPLD Firmware

VCCIO Selection Jumper

The Carrier Board VCCIO for the PL IO-banks of the mounted SoM are selectable by the jumpers J6 and J7.

...

VCCIO
vs. Voltage Levels		VCCIO_13VCCIO_33Note
1.8VJ7:pins 1-2J6: pins 1-2-
2.5VJ7: pins 3-4J6: pins 3-4-
3.3VJ7: pins 5-6J6: pins 5-6-

Table 16: VCCIO jumper settings.

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The maximum power consumption of the Carrier Board depends mainly on the mounted SoM's FPGA design running on the Zynq chipdevice.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

...

Figure 3: Board power distribution diagram.

Power Rails

The voltage direction of the power rails is directed at on-board connectors' view:

Module Connector Module Connector (B2B) DesignatorVCC / VCCIODirectionPinsNotes
JB1

VIN33

Out

Pin 1, 2, 3, 4, 5, 6

3.3V module supply voltage
VCCIO_13OutPin 101, 102PL IO-bank VCCIO
VCCIO_33OutPin 29, 30PL IO-bank VCCIO
3.3VInPin 65, 66voltage output from module
JB2

1.8V

In

Pin 49

voltage output from module
2.5VInPin 13voltage output from module
USB-VBUSOutPin 107USB Host supply voltage
VBAT_INOutPin 118RTC buffer voltage

Table 19: Power pin description of B2B Module Connector.

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Jumper / Header DesignatorVCC / VCCIODirectionPinsNotes
J6VCCIO_33OutInPin 2, 4, 6-
1.8VInOut5-
2.5VInOut3-
3.3VInOut1-
J7

VCCIO_13

OutInPin 2, 4, 6-
1.8VInOut5-
2.5VInOUt3-
3.3VInOut1-

Table 20: Power Pin description of VCCIO selection jumper pin header.

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Main Power Jack and Pins DesignatorVCC / VCCIODirectionPinsNotes
J125VINIn

-

-
J95VINInPin A1, A2'5VIN' power supply to the Carrier Board as alternative to J12
J2VBAT_INInPin 1Attention: Pin 2 connected to ground. VBAT_IN voltage on this pin cause short-circuit.

Table 21: Main Power jack and pins description.

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In

1

-
J95VINIn / OutA1, A2also usable as '5VIN' power supply to the Carrier Board as alternative to J12
J2VBAT_INIn1Attention: Pin 2 connected to ground. VBAT_IN voltage on this pin cause short-circuit.

Table 21: Main Power jack and pins description.


Peripheral Socket DesignatorVCC / VCCIODirectionPinsNotes
J10 / J11USB-VBUSIn / Out1Direction depends on USB2.0 mode
J1VIN33Out4MikroSD Card socket VDD

Table 22: Power pin description of peripheral connector.


XMOD Header DesignatorVCC / VCCIODirectionPinsNotes
JB33.3V-5not connected
VIOOut6connected to VIN33

Table 23: Power pin description of XMOD/JTAG Connector.

Board to Board Connectors

The TE0729 module has two 120-pin double-row REF-189019-02 connectors on the bottom side which are compatible with Samtec BSE-060-01-L-D-A connectors. Mating connectors on the baseboard are REF-189019-01, which are compatible with Samtec BTE-060-01-L-D-A connectors.

Order
number

REF NumberSamtec NumberTypeMated HeightData sheetComment
-REF-189019-02BTE-060-01-L-D-A-K-TRModule connector5 mmhttp://suddendocs.samtec.com/catalog_english/bte.pdfStandard connector
used on module
26663REF-189019-01BSE-060-01-L-D-A-TRBaseboard connector5 mmhttp://suddendocs.samtec.com/catalog_english/bse.pdfStandard connector
used on board

Table 24: B2B Connectors.


Connector SpecificationsValue
Insulator materialLiquid crystal polymer
Stacking height5 mm
Contact materialPhosphor-bronze
PlatingAu or Sn over 50 μ" (1.27 μm) Ni
Current rating2 A per pin (1 pin powered per row)
Operating temperature range-55 °C to +125 °C
Voltage rating225 VAC with 5 mm stack height
Max cycles100
RoHS compliantYes

Table 25: B2B Connector specifications.

Table 22: Power pin description of peripheral connector.

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Table 23: Power pin description of XMOD/JTAG Connector.

Board to Board Connectors

Include PageIN:Samtec LSHMIN:Samtec LSHM

Variants Currently In Production

 Module Variant

Operating Temperature

USB SocketTemperature Range
TEB0729-0203-A-40°C to +125°CUSB2.0 Type A socket fittedIndustrial
TEB0729-0203-B-40°C to +125°CMicro USB2.0 B socket fittedIndustrial

Table 2426: Module Board variants.

Technical Specifications

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Parameter

MinMax

Units

Reference Document

5VIN supply voltage

 -0.3 7

V

MP5010A, EN6347QI data sheet

Storage temperature

 -65

150

°C

-

Table 2527: Module absolute maximum ratings.

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ParameterMinMaxUnitsReference Document
5VIN supply voltage 4.755.25 VUSB2.0 specification concerning 'VBUS' voltage
Operating temperature -40125°C-

Table 2628: Module recommended operating conditions.

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Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
-

01

First Production Release

 -TEB0729-01
Documentation Link
-

01

  • First Production Release
 -TEB0729-01
-02
  • Second Production Release
  • HW-Modification since 22.08.2017
  • Refer to Changes list in Schematic

    for further details in changes to REV01

-TEB0729-02
-03
  • Rework Reset-Signals by Pin-Swap
  • Refer to Changes list in Schematic for
    further details in changes to REV02
-02Second Production Release
-TEB0729-0203

Table 2729: Module hardware revision history.

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Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd



Ali Naseri
  • update TRM to board revision 03

2017-10-27

v.14
Ali Naseri
  • initial document to board revision 02

Table 2830: Document change history.

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