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Note
JTAG interface is not directly available to FX2 microcontroller.

Configuration Mode is selected by mode select pins (M[2:0] or M[1:0]) values

The mode select pins, M[2:0] for Spartan-3E and Spartan-3A (M[1:0] for Spartan-6), define the configuration mode that the FPGA uses to load its bitstream, as shown in Table 2-1. The logic levels applied to the mode pins is sampled on the rising edge of INIT_B, immediately after the FPGA completes initializing its internal configuration memory. Functional Differences between Spartan-3 Generation Families summarizes the slight differences in functionality between the Spartan-3/6 generation families.

Scroll Title
titleMode Pin Settings and Associated FPGA Configuration Mode by Family
Spartan 6 FPGA FamilySpartan 3 FPGA Family
M[1:0]Spartan-6M[2:0]

Spartan-3E

Spartan-3A DSP

<0:1>

Master Serial/SPI Mode<0:0:0>Master Serial (Platform Flash) Mode (1)
<0:0:1>Master SPI Mode

<0:0>

Master SelectMAP/BPI (1)<0:1:0>BPI Up (1)
<0:1:1>BPI Down (1)Reserved
It does not exist

<1:0:0>

Reserved
<x:x>JTAG Mode
always available		<1:0:1>

JTAG Mode,
should be selected

<1:0>

Slave Parallel (SelectMAP) Mode<1:1:0>Slave Parallel (SelectMAP) Mode
<1:1>Slave Serial Mode<1:1:1>Slave Serial Mode

(1) It is a mode not available in TE USB FX2 modules

Info
Among the available modes, Master SPI Mode and JTAG Mode do NOT require support from USB FX2 microcontroller reference firmware; it is only necessary that this two modes do not have interference from this firmware.
Info
Among the available modes, Slave Parallel (SelectMAP) Mode and Slave Serial Mode require support from USB FX2 microcontroller firmware; this happens, because it is the only available host (on the TE USB FX2 module) to write configuration data into FPGA and the USB FX2 module could retrieve data from various sources: SPI Flash, USB connection and B2B connection.
Note
USB FX2 microcontroller reference firmware does NOT support Slave Parallel (SelectMAP) Mode and/or Slave Serial Mode; if the user needs to use these configuration modes, he/she should write a custom firmware that load the configuration data from a source (SPI Flash, USB connection or B2B connection) and write the retrieved configuration data in the FPGA.

Master SPI Mode (TE0320 and TE0300, Bus Width=1) or Master Serial/SPI (TE0630, Bus Width=1,2 or 4)

FPGA configures itself from an attached industry-standard (third-party) SPI serial Flash PROM. The FPGA supplies the CCLK output clock from its internal oscillator and drives the clock input of the attached SPI Flash PROM. 

JTAG Mode

When the FPGA mode pins are set for JTAG mode (M[2:0] = <1:0:1> in TE0320 and TE0300 module), the FPGA waits to be configured via the JTAG port after a power-on event or after PROG_B is pulsed Low. Selecting the JTAG mode simply disables the other configuration modes. No otherpins are required as part of the configuration interface.

While there is no specific mode for JTAG (in TE0630 module), the JTAG interface is available as a configuration interface any time the device is powered.

Slave Parallel (SelectMap) Mode

When using Slave Parallel mode configuration, an external host, such as a microprocessor or microcontroller (the USB FX2 microcontroller for the TE USB FX2 module), writes byte-wide configuration data  (16 bit are not available in TE USB FX2 modules) into the FPGA, using a typical peripheral interface. See "Slave Parallel (SelectMAP) Mode" of ug332 or "SelectMAP Configuration Interface" of ug380.

Slave Serial Mode

In Slave Serial mode, an external host such as a microprocessor or microcontroller (the USB FX2 microcontroller for the TE USB FX2 module) writes serial configuration data into the FPGA, using a synchronous serial interface.

TE0630

Scroll Title
titleTE0630 Configuration Mode and FPGA image source available

Spartan-6 (TE0630 module)

Source of FPGA image (bitstream). It could be retrieved from

M[1:0]

Configuration Mode

Bus Width

CCLK Direction
(FPGA based)		TE0630's SPI Flash
memory		TE0630's Jtag
connection		TE0630's USB
connection		TE0630's B2B
connection
WITHOUT HW modification (desoldering/resoldering) of U15, Y18 connection with 3.3V and Gnd, it is only possible to use two type of configurations.
<0:1>Master Serial/SPI1,2 or 4Output(tick)(error)(error)(error)
<x:x> (1)JTAG Mode1Input (TCK)(error)(tick)

(error) (2)

(tick) 
WITH HW modification (desoldering/resoldering) of U15, Y18 connection with 3.3V and Gnd, it is only possible to use two type of configurations.
<1:0>Slave Parallel (SelectMap) Mode8 (3)Input(tick)(error) (4)(tick)(tick)
<1:1>Slave Serial Mode1Input(tick)(error) (4)(tick)(tick)

LEGEND:

  • (tick) this symbol means that the FPGA image (bitstream) could be retrieved from  the source corrispondent to the column, using the Configuration Mode corrispondent to the row
  • (error) this symbol means that the FPGA image (bitstream) could NOT be retrieved from the source corrispondent to the column, using the Configuration Mode corrispondent to the row

(1) Spartan-6 devices also have a dedicated four-wire JTAG (IEEE Std 1149.1) port that is always available to the FPGA regardless of the mode pin settings.

(2) Do not confuse this connection with the Jtag-USB cable used with TE0630's Jtag connection.

(3) 16 bit inteface is theoretically possble but is not supported in the TE0630 module.

(4) TDI,TDO,TCK and TMS are not connected to USB FX2 microcontroller.

Another configuration is theoretically possible, but this configuration requires a component not mounted on the TE0630 module.

Scroll Title
titleConfiguration modes unavailble because they require a component not mounted on the TE0630 module


M[1:0]

Spartan-6 (TE0630 module)
Configuration Mode

Component required
(not mounted on TE0630 module)
<0:0>

Master SelectMAP/BPI

third-party BPI Flash

TE0320

See TE0320 Mode Select Pins M[2:0].

Scroll Title
titleTE0320 Configuration Mode and FPGA image source available


Spartan-3A DSP (TE0320 module)

Source of FPGA image (bitstream). It could be retrieved from
M[2:0]

Configuration Mode

Bus Width

CCLK Direction
(FPGA based)		TE0320's SPI Flash
memory		TE0320's Jtag
connection		TE0320's USB
connection		B2B
connection
<0:0:1>Master SPI Mode1Output(tick)(error)(error)(error)
<1:0:1>JTAG Mode1Input (TCK)(error)(tick)

(error) (1)

(tick) 
<1:1:0>Slave Parallel (Select MAP) Mode8Input(tick)(error) (2)(tick)(tick)
<1:1:1>Slave Serial Mode1Input(tick)(error) (2)(tick)(tick)

LEGEND:

  • (tick) this symbol means that the FPGA image (bitstream) could be retrieved from  the source corrispondent to the column, using the Configuration Mode corrispondent to the row
  • (error) this symbol means that the FPGA image (bitstream) could NOT be retrieved from the source corrispondent to the column, using the Configuration Mode corrispondent to the row

(1) Do not confuse this connection with the Jtag-USB cable used with TE0320's Jtag connection.

(2) TDI,TDO,TCK and TMS are not connected to USB FX2 microcontroller.

Other 2 configurations are theoretically possible, but these configurations require a component not mounted on the TE0320 module.

 

Scroll Title
titleConfiguration modes unavailble because they require a component not mounted on the TE0320 module


M[2:0]

Spartan-3A DSP (TE0320 module)
Configuration Mode

Component required
(not mounted on TE0320 module)
<0:0:0>Master Serial (Platform Flash) ModeXilinx Platform Flash
<0:1:0>BPI Upthird-party BPI Flash

TE0300

See TE0300 DIP Slide Switch S4 (Configuration).

Scroll Title
titleTE0300 Configuration Mode and FPGA image source available

Spartan-3E  (TE0300 module)

FPGA image (bitstream) could be retrieved from

M[2:0]

Configuration Mode

Bus Width

CCLK Direction

(FPGA based)

TE0300's SPI Flash
memory		TE0300's Jtag
connection		TE0300's USB
connection		B2B
connection
WITHOUT HW modification (desoldering/resoldering) of M10, V11 connection with 3.3V and Gnd, it is only possible to use two type of configurations.
<0:0:1>Master SPI Mode1Output(tick)(error)(error)(error)
<1:0:1>JTAG Mode1Input (TCK)(error)(tick)

(error) (1)

(tick) 
WITH HW modification (desoldering/resoldering) of M10, V11 connection with 3.3V and Gnd, it is also possible to use these two type of configurations.
<1:1:0>Slave Parallel (Select MAP) Mode8Input(tick)(error) (2)(tick)(tick)
<1:1:1>Slave Serial Mode1Input(tick)(error) (2)(tick)(tick)

LEGEND:

  • (tick) this symbol means that the FPGA image (bitstream) could be retrieved from  the source corrispondent to the column, using the Configuration Mode corrispondent to the row
  • (error) this symbol means that the FPGA image (bitstream) could NOT be retrieved from the source corrispondent to the column, using the Configuration Mode corrispondent to the row

(1) Do not confuse this connection with the Jtag-USB cable used with TE0300's Jtag connection.

(2) TDI,TDO,TCK and TMS are not connected to USB FX2 microcontroller.

Other 3 configurations are theoretically possible, but these configuration modes require a component not mounted on the TE0300 module.

Scroll Title
titleConfiguration modes unavailble because they require a component not mounted on the TE0300 module.


M[2:0]

Spartan-3E (TE0300 module)
Configuration Mode

Component required
(not mounted on TE0300 module)
<0:0:0>Master Serial (Platform Flash) ModeXilinx Platform Flash
<0:1:0>BPI Upthird-party BPI Flash
<0:1:1>BPI Downthird-party BPI Flash