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JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on B2B. In the carrier board TEB0835 can be activated this pin with S1-4 dip switch.
| CPLD_JTAGEN (B2B J1-30) | S1-4 on TEB0835 Carrier Board | Description |
|---|---|---|
| 0 | OFF | FPGA access |
| 1 | ON | CPLD access |
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