Page History
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Product Specification
Port Description
| Name / opt. VHD Name | Direction | Pin | Bank Power | Description |
|---|---|---|---|---|
| MIO13 | out | 36 | 1.8V_CPLD | Output to drive gate of MOSFET transistor for Status-LED |
| MODE0 | out | 35 | 1.8V_CPLD | ZynqMP boot mode pin 0 |
| PG_VCCRF | in | 34 | 1.8V_CPLD | Power Good input from PWR_PRE |
| SRST_B | out | 33 | 1.8V_CPLD | FPGA external system reset / currently_not_used |
| PROG_B | out | 32 | 1.8V_CPLD | FPGA reset PL configuration logic |
| PG_GR2 | in | 31 | 1.8V_CPLD | Power control input from PWR_PS and PWR_DDR |
| MIO28_UART1_TX | out | 29 | 1.8V_CPLD | UART Transmition pin |
| MIO28_UART1_RX | in | 28 | 1.8V_CPLD | UART Receive pin |
| FPGA_IO0 | inout | 27 | 1.8V_CPLD | FPGA GPIO / currently_not_used |
| FPGA_IO1 | inout | 26 | 1.8V_CPLD | FPGA GPIO / currently_not_used |
| EN_PS_PL | out | 14 | 3.3V_CPLD | Power enable for PWR_CORE , PWR_PS and PWR_GT |
| EN_GR1 | out | 15 | 3.3V_CPLD | Power enable for PWR_GT and PWR_PS |
| EN_RF_ADC | out | 16 | 3.3V_CPLD | Power enable for PWR_ADC |
| PG_RF_DAC | in | 17 | 3.3V_CPLD | Power control input from PWR_DAC |
| EN_VCCRF | out | 18 | 3.3V_CPLD | Power enable for PWR_PRE |
| EN_GR2 | out | 19 | 3.3V_CPLD | Power enable for PWR_DDR , PWR_GT and PWR_PS |
| PG_PS_PL | in | 20 | 3.3V_CPLD | power control input from PWR_CORE , PWR_GT and PWR_PS |
| PG_GR1 | in | 21 | 3.3V_CPLD | Power control input from PWR_GT and PWR_PS |
| PG_RF_ADC | in | 23 | 3.3V_CPLD | Power control input from PWR_ADC |
| EN_RF_DAC | out | 24 | 3.3V_CPLD | Power enable for PWR_DAC |
| MODE2 | out | 2 | 1.8V_CPLD | ZynqMP boot mode pin 2 |
| MODE1 | out | 3 | 1.8V_CPLD | ZynqMP boot mode pin 1 |
| POR_B | out | 4 | 1.8V_CPLD | Power-On reset signal |
| MODE3 | out | 5 | 1.8V_CPLD | ZynqMP boot mode pin 3 |
| INIT_B | in | 7 | 1.8V_CPLD | FPGA PL initialization activity and configuration error signal / currently_not_used |
| F_TDI | out | 8 | 1.8V_CPLD | JTAG ZynqMP |
| F_TMS | out | 9 | 1.8V_CPLD | JTAG ZynqMP |
| F_TCK | out | 10 | 1.8V_CPLD | JTAG ZynqMP |
| F_TDO | in | 11 | 1.8V_CPLD | JTAG ZynqMP |
| DONE | in | 12 | 1.8V_CPLD | FPGA PL configuration done indicator / currently_not_used |
| JTAG_TDO | out | 48 | 3.3V_CPLD | JTAG_B2B |
| JTAG_TDI | in | 47 | 3.3V_CPLD | JTAG_B2B |
| JTAG_TCK | in | 45 | 3.3V_CPLD | JTAG_B2B |
| JTAG_TMS | in | 44 | 3.3V_CPLD | JTAG_B2B |
| CPLD_IO0 | in | 43 | 3.3V_CPLD | BOOT Mode input pin 0 |
| CPLD_IO1 | in | 42 | 3.3V_CPLD | BOOT Mode input pin 1 |
| CPLD_JTAGEN | in | 41 | 3.3V_CPLD | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) |
| CPLD_IO2 | inout | 40 | 3.3V_CPLD | CPLD IO / currently_not_used |
| CPLD_IO3 | inout | 38 | 3.3V_CPLD | CPLD IO / currently_not_used |
| RESETN | in | 37 | 3.3V_CPLD | Reset pin of CPLD (Active low) |
Functional Description
JTAG
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on B2B. In the carrier board TEB0835 can be activated this pin with S1-4 dip switch.
| CPLD_JTAGEN | S1-4 on TEB0835 Carrier Board | Description |
|---|---|---|
| 0 | OFF | FPGA access |
| 1 | ON | CPLD access |
Power
In this module the CPLD is responsible for controlling the power of the module. There are different power regulators or DC/DC converters whose outputs can be controlled by an enable signal. At the same time the outputs can also be monitored by power-good signals.
| Enable Signal |
|---|
| Power Good Signal | Schematic page |
|---|
| Net |
|---|
| Domain | Regulator/ DC-DC Converter |
|---|
| in/out |
|---|
| Voltage |
|---|
| EN_PS_PL |
| PG_PS_PL |
PWR_CORE PWR_PS PWR_GT |
LTM4662EY
LTM4644EY
TPS82085
5V/0.835V
5V/0.85V
5V/0.9VVCCINT, VCINT_IO, VCCBRAM PSINTLP/PSINTFP,PSINTFP_DDR MGTAVCC | PL PS_LP/PS_FP GTH | LTM4662EY LTM4644EY TPS82085 | 5V/0.835V 5V/0.85V 5V/0.9V | |
| EN_GR1 |
| PG_GR1 |
PWR_PS PWR_GT PWR_GT |
TPS82085
EP53A7LQIEN6347QI
5V/1.8V
5V/0.85V
5V/1.2V
PSAUX,PSADC,PSIO/VCCAUX,VCCAUX_IO/PS_DDR_PLL PSMGTRAVCC/MGTVCCAUX PSPLL/MGTAVTT | PS_LP/PL/PS_FP PS_FP/GTH PS_LP/GTH | TPS82085 EP53A7LQI EN6347QI | 5V/1.8V 5V/0.85V 5V/1.2V |
| EN_GR2 |
| PG_GR2 |
PWR_PS PWR_GT PWR_DDR PWR_DDR | VCC_B88_HD PS_MGTRAVTT DDR_2V5 DDR_1V2 | PS_LP PS_FP DDR DDR | TPS82085 EP53A7HQI TPS82085 TPS82085 | 5V/3.3V 5V/1.8V 5V/2.5V 5V/1.2V |
VCC_B88_HD
PS_MGTRAVTT
PS_LP
PS_FP
DDR
DDR
| EN_VCCRF |
| PG_VCCRF |
| PWR_PRE | VCCINT_AMS, APRE_1V15, APRE_3V3 | ADC and DAC | LTM4644EY | 5V/0.8534V,1.15V,3.3V |
| EN_RF_ADC |
| PG_RF_ADC |
PWR_ADC PWR_ADC |
ADC_AVCC ADC_AVCCAUX | ADC ADC | TPS74401 TPS74401 | 1.15V/0.925V 3.3V/1.8V |
ADC_AVCC
ADC_AVCCAUXADC
ADC
| EN_RF_DAC |
| PG_RF_DAC |
PWR_DAC PWR_DAC PWR_DAC |
DAC_AVCC DAC_AVCCAUX DAC_AVTT | DAC DAC DAC | TPS74801 TPS74801 TPS74801 | 5V/0.925V 5V/1.8V 5V/2.5V |
Power-on Sequencing
According to the Xilinx instructions the power regulator or DC-DC converter must be switched on or off in a certain order. This is called power-on or power-off sequencing.To implement power-on sequencing correctly, a state machine must be running there. In the following you can see the State Machine Diagram.
LED
| Power Stage | Blink Sequence | Comment |
|---|---|---|
| IDLE | ***************o | Power Sequencing can not start |
| Stage 0 | *************o*o | One of the following nets are failed: VCCINT, VCINT_IO, VCCBRAM, PSINTLP, PSINTFP, PSINTFP_DDR, MGTAVCC |
| Stage 1 | ***********o*o*o |
DAC_AVCC
DAC_AVCCAUX
DAC_AVTT
DAC
DAC
DAC
Power-on Sequencing
Boot Mode
| One of the following nets are failed: PSAUX, PSADC, PSIO, VCCAUX, VCCAUX_IO, PS_DDR_PLL, PSMGTRAVCC, MGTVCCAUX, PSPLL, MGTAVTT | ||
| Stage 2 | *********o*o*o*o | One of the following nets are failed: VCC_B88_HD, PS_MGTRAVTT, DDR_2V5 , DDR_1V2 |
| Stage 3 | *******o*o*o*o*o | One of the following nets are failed: VCCINT_AMS, APRE_1V15, APRE_3V3 |
| Stage 4 | *****o*o*o*o*o*o | One of the following nets are failed: ADC_AVCC, ADC_AVCCAUX, DAC_AVCC, DAC_AVCCAUX, DAC_AVTT |
| WAIT_RDY | ***o*o*o*o*o*o*o | One of the last stages is not ok |
| RDY | oooooooooooooooo | Power is ok |
Boot Mode
Boot Modes can be selected via B2B Pin Mode.
| B2B Pin J1-28 (CPLD IO1) | B2B Pin J1-26 (CPLD IO0) |
|---|
| Boot Mode | |
|---|---|
| 0 | 0 |
| Boot from PS JTAG | |
| 0 | 1 |
| Boot from QSPI | |
| 1 | 1 |
| Boot from SD Card |
Appx. A: Change History and Legal Notices
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| REV00 | REV01 |
| Work in progress | 2017-06-07 | | Page info | | created-user | created-user | Initial release||||||||||||||||||||||||
| All |
|
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