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When state = RDY and DONE = '1' then FPGA_IO1 (pin number AE16 of the Xilinx FPGA on the RFSoC Module) connected with CPLD_IO2 (DIP SWITCH) else FPGA_IO1 is high impedance ('Z'). When DONE = '1' then en1='1' then PWR_STATUS <= FPGA_IO0 else PWR_STATUS blinks according to the state. The FPGA_IO0 is the pin number AE18 of the Xilinx FPGA on the RFSoC Module. The following table shows the relationship between user pins in the board when the FPGA is programmed successfully (DONE = '1'). Please note that the connected pins after programming the FPGA is only valid if the FPGA is programmed correctly and the power state in the CPLD code is RDY.

Boot Mode

Boot Modes can be selected via B2B Pin Mode.

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