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- The period for erery blink (*o) is 0.5sec.
User IO
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- FPGA_IO1 (
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- AE16 of
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- RFSoC
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- ) is connected with CPLD_IO2 (
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- S1-3 Dip switch on the carrier board) when the FPGA is programmed correctly otherweise this pin is high impedance
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- . After programming of the FPGA can user control this pin himself.
- FPGA_IO0 (AE18 of RFSOC) is connected with LED on the RFSoC module (D1) if the FPGA is programmed completely otherweise this LED (D1) blinks according to the power stage of the power-on sequencing of the FPGA.
| Component | Designator | Pin Name | Pin Number | Board | Interface | Connected in the Hardware with | Designator | Pin Name | Pin Number | Board | after programming the FPGA connected with | Designator | Pin Name | Pin Number | Board |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dip Switch | S1-3 | CPLD_IO2 | --- | TEB0835 | B2B | CPLD | U31 | CPLD_IO2 | 40 | TE0835 | FPGA | U1 | FPGA_IO1 | AE16 | TE0835 |
| FPGA | U1 | FPGA_IO0 | AE18 | TE0835 | --- | CPLD | U31 | FPGA_IO0 | 27 | TE0835 | LED | D1 | --- | --- | TE0835 |
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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| REV01 | REV02, REV01 |
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| 2020-08-18 | v.4 | REV00 | REV01 | Ivan Girshchenko / Mohsen Chamanbaz |
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| All |
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