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Template Revision 2.9 - on construction Design Name always "TE Series Name" + optional CPLD Name + "CPLD"
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Overview
Firmware for PCB CPLD with designator U39. Second CPLD Device in Chain: LCMX02-1200HC
Feature Summary- Power Management
- ...
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
Port Description
| Name / opt. VHD Name | Direction | Pin | Pullup/Down | Bank Power | Description |
|---|---|---|---|---|---|
| ALERT_N | in | B33 | UP | +3.3V_STB | Digital output . Interrupt or SMBus alert output. Can be configured as a second THERM output. (Pulled up) [U43,U47,U52,U57,U4](TMP461AIRUNT),U61(LM96163CISD/NOPB) |
| CPLD_DEBUG0 | out | A41 | |||
| CPLD_DEBUG1 | out | A2 | |||
| CPLD_DEBUG2 | out | B1 | |||
| CPLD_DEBUG3 | out | A3 | |||
| CPLD_HD0 | ? | B3 | |||
| CPLD_HD1 | ? | B28 | |||
| EN_VCCINT | out | B22 | |||
| EN_VTT_DDR | out | A22 | |||
| EN+0.85V_GT_AVCC_PS | out | B21 | |||
| EN+0.9V_GT_AVCC | out | B14 | |||
| EN+1.0V | out | A46 | |||
| EN+1.2V_DDR | out | A34 | |||
| EN+1.2V_GT_AVTT | out | B16 | |||
| EN+1.2V_PLL_PS | out | A15 | |||
| EN+1.3V_MGT_PS | out | B15 | |||
| EN+1.8V | out | B13 | |||
| EN+1.8V_AUX | out | A30 | |||
| EN+1.8V_GT_AVTT_PS | out | B20 | |||
| EN+2.5V_DDR | out | A44 | |||
| EN+2V_MGT_PS | out | A21 | |||
| EN+3.3V | out | B18 | |||
| EN+5V_BIAS | out | A17 | |||
| EXT_STATUS_LED_G | out | B9 | |||
| EXT_STATUS_LED_R | out | A25 | |||
| FAN_EN | out | B29 | |||
| FPGA_DONE | in | A24 | |||
| FTDI_PWR_EN_N | in | A36 | |||
| FTDI_RX | out | A35 | |||
| FTDI_TCK | in | A45 | |||
| FTDI_TDI | in | A47 | |||
| FTDI_TDO | out | A48 | |||
| FTDI_TMS | in | B34 | |||
| FTDI_TX | in | B27 | |||
| GND | A19 | ||||
| GND | -- | A39 | |||
| GND | -- | B11 | |||
| GND | -- | B31 | |||
| GND | -- | C1 | |||
| I2C_SCL_CPLD | B32 | ||||
| I2C_SDA_CPLD | A42 | ||||
| JTAGEN | in | B30 | |||
| MIO30_UART0_RXD | A8 | ||||
| MIO31_UART0_TXD | A9 | ||||
| MIO32_UART1_TXD | B8 | ||||
| MIO33_UART1_RXD | B7 | ||||
| MR / POR_B | outMR | A26 | |||
| NetU68_B2 | B2 | ||||
| PG_VCCINT | in | B23 | |||
| PG+0.85V_GT_AVCC_PS | in | B12 | |||
| PG+0.9V_GT_AVCC | in | A18 | |||
| PG+1.0V | in | B35 | |||
| PG+1.2V_DDR | in | A33 | |||
| PG+1.2V_GT_AVTT | in | A11 | |||
| PG+1.2V_PLL_PS | in | A28 | |||
| PG+1.3V_MGT_PS | in | A20 | |||
| PG+1.8V | in | B25 | |||
| PG+1.8V_AUX | in | A27 | |||
| PG+1.8V_AUX_PS | in | B10 | |||
| PG+1.8V_GT_AUX | in | A13 | |||
| PG+1.8V_GT_AVTT_PS | in | A16 | |||
| PG+2.5V_DDR | in | A32 | |||
| PG+2.5V_PL_DDR | in | A38 | |||
| PG+2V_MGT_PS | in | A1 | |||
| PG+3.3V | in | A23 | |||
| PWR_BTN | in | A12 | |||
| PWR_STAT_GRN | out | B24 | |||
| PWR_STAT_RED | out | A31 | |||
| SRST_B | inout | B5 | |||
| TCK | out | A5 | |||
| TDI | out | B4 | |||
| TDO | in | A6 | |||
| THERM_N | in | A40 | |||
| TMS | out | A7 |
Functional Description
JTAG
Power
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Appx. A: Change History and Legal Notices
Revision Changes
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
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Legal Notices
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Overview
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