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Template Revision 2.9 - on construction

Design Name always "TE Series Name" + optional CPLD Name + "CPLD"

  • Change List 1.9.1 to 2.0
    • add fix table of content
    • add table size as macro
    • removed page initial creator

Overview

Lattice MachXO2-4000HC is a CPLD chip, that is used in TEB0912 board as a system management controller. The system controller implements power management same as power sequencing, monitoring of input current and regulator outputs. Rather than power management is the system controller responsible for reset generation, zynq initial configuration, communication between temperture sensors and FPGA. System controller contains of some additional features same as watchdog timer, i2c interface, CAN bus and SMbus. The firmware of CPLD contains of various subsystems same as i2c master and i2c slave subsystems. I2c master reads the data of current sensor and 7 temperature sensors  , that measure the temperature of DC-DC converter chips. I2c slave is responsible for communicating with FPGA to write the measured data in FPGA.

Feature Summary

  • Power Management
  • Reset Management
  • JTAG Routing
  • Boot Mode
  • User IOs
  • LED and power state display
  • I2C interface
  • Watchdog timer
  • I2C to GPIO Master/Slave

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinPullup/DownBank PowerDescription
ALERT_NinB33UP+3.3V_STBDigital output . Interrupt or SMBus alert output of temperature sensors (TMP461AIRUNT- U43,U47,U52,U57,U4) and temperature sensor with integrated fan control (LM96163-U61) 
CPLD_DEBUG0outinA41UP+3.3V_STBCPLD debug pin 0
CPLD_DEBUG1outinA2UP+3.3V_STBCPLD debug pin 1
CPLD_DEBUG2outinB1UP+3.3V_STBCPLD debug pin 2
CPLD_DEBUG3outinA3NONE+3.3V_STBCPLD debug pin 3
CPLD_HD0outB3UP+3.3V_STBHigh density IOs select 0
CPLD_HD1outB28UP+3.3V_STBHigh density IOs select 1
EN_VCCINToutB22DOWN+3.3V_STBEnable pin for +0.85V DC-DC converter (LTM4630EY-U42A)
EN_VTT_DDRoutA22DOWN+3.3V_STBEnable pin for 2A Peak Sink/Source DDR Termination Regulator (TPS51206-U2, U3)
EN+0.85V_GT_AVCC_PSoutB21DOWN+3.3V_STBEnable pin for 1.5A low-dropout linear regulator (TPS74801DRC-U45)
EN+0.9V_GT_AVCCoutB14DOWN+3.3V_STBEnable pin for quad DC-DC microModule regulator with configurable 4A output array  for +0.9V output voltage (LTM4644EY-U44)
EN+1.0VoutA46DOWN+3.3V_STBEnable pin for 1.5A low-dropout linear regulator with +1.0V output voltage (TPS74801DRC-U13)
EN+1.2V_DDRoutA34DOWN+3.3V_STBEnable pin for quad DC-DC microModule regulator with configurable 4A output array  for +1.2V output voltage (LTM4644EY-U53)
EN+1.2V_GT_AVTToutB16DOWN+3.3V_STBEnable pin for quad DC-DC microModule regulator with configurable 4A output array  for +1.2V output voltage (LTM4644EY-U48)
EN+1.2V_PLL_PSoutA15DOWN+3.3V_STBEnable pin for 1.5A low-dropout linear regulator (TPS74801DRC-U46)
EN+1.3V_MGT_PSoutB15DOWN+3.3V_STBEnable pin for quad DC-DC microModule regulator with configurable 4A output array for +1.37V output voltage (LTM4644EY-U44) 
EN+1.8VoutB13DOWN+3.3V_STBEnable pin for quad DC-DC microModule regulator with configurable 4A output array  for +1.8V output voltage (LTM4644EY-U53)
EN+1.8V_AUXoutA30DOWN+3.3V_STBEnable pin for 1.5A low-dropout linear regulator with +1.8V output voltage  (TPS74801DRC-U49,U50,U51)
EN+1.8V_GT_AVTT_PSoutB20DOWN+3.3V_STBEnable pin for 1.5A low-dropout linear regulator with +1.8V output voltage  (TPS74801DRC-U54)
EN+2.5V_DDRoutA44DOWN+3.3V_STBEnable pin for 1.5A low-dropout linear regulator with +2.5V output voltage  (TPS74801DRC-U55, U56)
EN+2V_MGT_PSoutA21DOWN+3.3V_STBEnable pin for quad DC-DC microModule regulator with configurable 4A output array  for +2.0V output voltage (LTM4644EY-U48)
EN+3.3VoutB18DOWN+3.3V_STBEnable pin for quad DC-DC microModule regulator with configurable 4A output array  for +3.3V output voltage (LTM4644EY-U1)
EN+5V_BIASoutA17DOWN+3.3V_STBEnable pin for low dropout linear regulator with +5V output voltage (ADP7102ACPZ-U58)
EXT_STATUS_LED_GoutB9NONE+3.3V_STBExternal status LED green (J40-Pin2)
EXT_STATUS_LED_RoutA25NONE+3.3V_STBExternal status LED red (J40-Pin3)
FAN_ENoutB29UP+3.3V_STBEnables a smart high-side power switch to drive the FAN (BTS41411N-U60)
FPGA_DONEinA24UP+3.3V_STBFPGA PL configuration done indicator
FTDI_PWR_EN_NinA36UP+3.3V_STBActive low power enable output of FTDI chip (FT2232H56Q-U38)
FTDI_RXoutA35NONE+3.3V_STBUART RXD of FTDI chip (FT2232H56Q-U38)
FTDI_TCKinA45NONE+3.3V_STBFTDI JTAG clock pin (FT2232H56Q-U38)
FTDI_TDIinA47NONE+3.3V_STBFTDI JTAG data input pin (FT2232H56Q-U38)
FTDI_TDOoutA48NONE+3.3V_STBFTDI JTAG data output pin (FT2232H56Q-U38)
FTDI_TMSinB34NONE+3.3V_STBFTDI JTAG mode select pin (FT2232H56Q-U38)
FTDI_TXinB27NONE+3.3V_STBUART TXD of FTDI chip (FT2232H56Q-U38)
I2C_SCL_CPLDinoutB32UP+3.3V_STBI2C clock pin that connected to all temperature sensors and current sensor
I2C_SDA_CPLDinoutA42UP+3.3V_STBI2C data pin that connected to all temperature sensors and current sensor
JTAGENinB30DOWN+3.3V_STBJTAG enable input pin of CPLD (Dip switch S4-1) If logical low, JTAG routed to FPGA. If logical high, CPLD access. 
MIO30_UART0_RXDinA8NONE+1.8VMIO30 pin of FPGA (XCZU11EG-1FFVC1760I- U30R)
MIO31_UART0_TXDoutA9NONE+1.8VMIO31 pin of FPGA (XCZU11EG-1FFVC1760I- U30R)
MIO32_UART1_TXDoutB8NONE+1.8VMIO32 pin of FPGA (XCZU11EG-1FFVC1760I- U30R)
MIO33_UART1_RXDinB7NONE+1.8VMIO33 pin of FPGA (XCZU11EG-1FFVC1760I- U30R)
MRoutA26UP+3.3V_STBManual-reset that connected to MR pin of ultralow supply-current voltage monitor chip (TPS3106K33DBVR-U73)
NetU68_B2
B2

/currently_not_used
PG_VCCINTinB23UP+3.3V_STBPower good pin for +0.85V DC-DC converter (LTM4630EY-U42A)
PG+0.85V_GT_AVCC_PSinB12UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator for +0.85V output voltage (TPS74801DRC-U45) 
PG+0.9V_GT_AVCCinA18UP+3.3V_STBPower good pin for quad DC-DC microModule regulator with configurable 4A output array  for +0.9V output voltage (LTM4644EY-U44)
PG+1.0VinB35UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator with +1.0V output voltage (TPS74801DRC-U13)
PG+1.2V_DDRinA33UP+3.3V_STBPower good pin for quad DC-DC microModule regulator with configurable 4A output array  for +1.2V output voltage (LTM4644EY-U53)
PG+1.2V_GT_AVTTinA11UP+3.3V_STBPower good pin for quad DC-DC microModule regulator with configurable 4A output array  for +1.2V output voltage (LTM4644EY-U48)
PG+1.2V_PLL_PSinA28UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator for +1.2V output voltage (TPS74801DRC-U46)
PG+1.3V_MGT_PSinA20UP+3.3V_STBPower good pin for quad DC-DC microModule regulator with configurable 4A output array  for +0.9V output voltage (LTM4644EY-U44)
PG+1.8VinB25UP+3.3V_STBPower good pin for quad DC-DC microModule regulator with configurable 4A output array  for +1.8V output voltage (LTM4644EY-U53)
PG+1.8V_AUXinA27UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator with +1.8V output voltage  (TPS74801DRC-U50)
PG+1.8V_AUX_PSinB10UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator with +1.8V output voltage  (TPS74801DRC-U51)
PG+1.8V_GT_AUXinA13UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator with +1.8V output voltage  (TPS74801DRC-U49)
PG+1.8V_GT_AVTT_PSinA16UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator with +1.8V output voltage  (TPS74801DRC-U54)
PG+2.5V_DDRinA32UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator with +2.5V output voltage  (TPS74801DRC-U55)
PG+2.5V_PL_DDRinA38UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator with +2.5V output voltage  (TPS74801DRC-U56)
PG+2V_MGT_PSinA1UP+3.3V_STBPower good pin for quad DC-DC microModule regulator with configurable 4A output array  for +2.0V output voltage (LTM4644EY-U48)
PG+3.3VinA23UP+3.3V_STBPower good pin for quad DC-DC microModule regulator with configurable 4A output array  with +3.3V output voltage (LTM4644EY-U1)
PWR_BTNinA12UP+3.3V_STBPower button input (J40-Pin1)
PWR_STAT_GRNoutB24NONE+3.3V_STBRed LED for power status display ( D11-Red)
PWR_STAT_REDoutA31NONE+3.3V_STBGreen LED for power status display (D12-Green)
SRST_BinoutB5UP+1.8VPS software reset (Active Low) (XCZU11EG-1FFVC1769I- U30S)
TCKoutA5NONE+1.8VZynq JTAG clock pin (XCZU11EG-1FFVC1760I- U30S)
TDIoutB4NONE+1.8VZynq JTAG data input pin (XCZU11EG-1FFVC1760I- U30S)
TDOinA6NONE+1.8VZynq JTAG data output pin (XCZU11EG-1FFVC1760I- U30S)
THERM_NinA40UP+3.3V_STBOvertemperature termal shutdown pin of temperature sensors ( TMP461, U43,U47,U52,U57,U4) and temperature sensor with integrated fan control (LM96163-U61)
TMSoutA7NONE+1.8VZynq JTAG mode select pin (XCZU11EG-1FFVC1760I- U30S)


Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA is be multiplexed via JTAGEN pin of CPLD (B30) (logical one for CPLD, logical zero for FPGA).

CPLD JTAGEN (Dip switch S4-1)Description
0FPGA access
1CPLD access

Power

In this board the CPLD is responsible for controlling and monitoring of power supply of the board. There are various DC-DC converter or regulators , one input current sensor and seven temperature sensors. To control every converter chip or regualtor monitors CPLD power good outputs of regulators or DC-DC converters continuously to avoid over-voltage in the power system. System controller reads the measured temperature of all temperature sonsors continuously to avoid over-temperature in regulators or DC-DC converter chips.

Enable SignalPower Good SignalDomainSchematic PageInput power NetRegulator/ DC-DC ConverterOutput power Net
EN+1.0VPG+1.0VPWR_PCIePCIe_Switch_PWR+1.37VTPS74801DRC+1.0V
EN+2.5V_DDRPG+2.5V_DDR
PG+2.5V_PL_DDR		PWR_DDR
PWR_DDR		POWER3
POWER3		+3.3V
+3.3V		TPS74801DRC
TPS74801DRC		+2.5V_DDR
+2.5V_PL_DDR
EN+1.8VPG+1.8V?POWER3+12VLMT4644EY+1.8V
EN+1.2V_DDRPG+1.2V_DDRPWR_DDRPOWER3+12VLMT4644EY+1.2V_DDR
EN+1.8V_AUX

PG+1.8V_AUX
PG+1.8V_GT_AUX
PG+1.8V_AUX_PS

?
PWR_GT
PWR_PS		POWER2
POWER2
POWER2		+2V_MGT_PS
+2V_MGT_PS
+2V_MGT_PS		TPS74801DRC
TPS74801DRC
TPS74801DRC		+1.8V_AUX
+1.8V_GT_AUX
+1.8V_AUX_PS
EN+1.2V_PLL_PSPG+1.2V_PLL_PSPWR_PSPOWER1+1.37VTPS74801DRC+1.2V_PLL_PS
EN+0.85V_GT_AVCC_PSPG+0.85V_GT_AVCC_PSPWR_GTPOWER1+1.37VTPS74801DRC+0.85V_GT_AVCC_PS
EN+1.8V_GT_AVTT_PSPG+1.8V_GT_AVTT_PSPWR_GTPOWER3+2V_MGT_PSTPS74801DRC+1.8V_GT_AVTT_PS
EN+1.2V_GT_AVTTPG+1.2V_GT_AVTTPWR_GTPOWER2+12VLTM4644EY+1.2V_GT_AVTT
EN+5V_BIAS--?POWER6+12VADP7102ACPZ-5.0-R7+5V_BIAS
EN+0.9V_GT_AVCC

PG+0.9V_GT_AVCC

PWR_GTPOWER1+12VLTM4644EY+0.9V_GT_AVCC
EN+1.3V_MGT_PSPG+1.3V_MGT_PSPWR_GTPOWER1+12VLTM4644EY+1.37V
EN+2V_MGT_PSPG+2V_MGT_PSPWR_GTPOWER2+12VLTM4644EY+2V_MGT_PS
EN_VTT_DDR---PWR_DDR
PWR_PS		POWER4+3.3V
+3.3V		TPS51206DSQ
TPS51206DSQ		VTT_DDR_PL
VTT_DDR_PS
EN+3.3VPG+3.3V?POWER4+12VLTM4644EY+3.3V
EN_VCCINTPG_VCCINTPWR_COREPOWER0+12VLTM4630EY+0.85V_VCCINT

Appx. A: Change History and Legal Notices

Revision Changes

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