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1 Overview

This guide shows the main components of the TE0802 module and introduces the first steps to get the provided reference design up and running. 

This module TE00802 has a Xilinx Zynq Ultrascale+ and several hardware features onboard that allows you to create digital hardware and software designs. For communication and configuration the module board offers a JTAG/UART Interface.

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1 Overview

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1 .1 Prerequisites

1.2 Getting Started with the TE0802

The module TE00802 has a Xilinx Spartan-7 FPGA onboard that allows you to create extensive digital hardware and software designs.

Most of the FPGA IOs are spread around the carrier. The TE0717 is assembled with HyperRAM (64 Mbit), QSPI non-volatile Flash memory (64 Mbit) and plenty of IOs which enable great hardware expandability. For communication and configuration the module board offers a JTAG/UART Interface.

This Getting Started Guide shows how to set up the board, attach the jumpers, wire it up and connect it with the software. The TE0802 Test Board description goes into "how to use the provided reference design" and in here we touch the aspect of how to add your own IP to the design. This includes changing the Vivado Block Design, regenerating the bitstream and using the hardware export(.xsa file) in Vitis to develop software that runs on the MicroBlaze.

1.2

Documentation

• Official links to the shop:
  • TE0802-02-1AEV2-A-MPSoC-Development-Board-mit-Xilinx-Zynq-UltraScale-ZU1-und-1-GB-LPDDR4
    
  • TE0802-02-2AEV2-A-MPSoC-Development-Board-mit-Xilinx-Zynq-UltraScale-ZU2-und-LPDDR4
• Technical Reference Manual:
  
  • TE0802 Technical Reference Manual
• Resources & Reference Designs:
  • TE0802 Resources
  • TE0802 Reference DesignsDesign

1.

3 Hardware Features

Firgure 2: TE0717+TEB0717 Hardware Blockdiagram

Basic IOs<->FPGA connections are as following, Table 1:

FPGA Pin

2 Board Power-Up

2.1 TE0802 Hardware Setup and Power up in QSPI-Boot mode (simple Hello Trenz application)

1. Download the source code and configuration files for "TE0802 test_board" reference design. Ensure that your download files match your Vivado version.
2. Check the settings from DIP-Switch S1 (JTAG):

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     S1.1	S1.2	S1.3	S1.4
     OFF	OFF	OFF	OFF

     
     

3. Connect the MicroUSB cable from your module board with your PC
4. Connect the module board with the power supply (5V)
5. Power on module board

6. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   Code Block
   language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh
   ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):

   
   

7. Press '0' and enter to start "Module Selection Guide"
   1. Select your assembly version
   2. validate selection
   3. press '1' and enter to "create Vivado project"

8. Program 'hello_te0802' application on QSPI flash

   Code Block
   language bash theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
   TE::pr_program_flash -swapp hello_te0802

   
   

9. Restart the module board

10. In case the QSPI Flash is loaded with the reference design, you can connect to the board with a program like PuTTY. Just open up a serial session with baudrate of 115200 and the right COM-port (visible in Device Manager).
    
    

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    anchor Figure_VHM title-alignment center title Terminal example
    Image AddedImage Added

    
    

2.2 TE0802 Hardware Setup and Power up in SD-Boot mode (Linux)

1. Check the settings from DIP-Switch S1:

2 Board Power-Up

2.1 TE0802 Hardware Setup and Power up

1. Check the Jumper setting
   
   

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   anchor Figure_VHM title-alignment center

   Figure 3: Jumper setting

   The Voltage set with Jumper J1 determines the source of the input voltage for the voltages regulator chip U1 to the left of J1. Either 5V from the MicroUSB port (VUSB) or 5V from pin header J4.

   With the shown setting of Jumper J2 the voltage VADJ is set to 3.3V that comes from the carriers voltage regulator chip U1. The 1.8V comes from the module. The Voltage VADJ is wired to the module and is used as the BANK34 supply voltage.

2. Use a MicroUSB cable to connect your board to the PC.cc

3. All the LEDs are simply routed to the FPGA, hence none of them should be turned on. If the qspi flash on the module is preloaded with a design though, it might be that some LEDs are blinking.

4. In case the QSPI Flash is loaded with the reference design, you can connect to the board with a program like PuTTY. Just open up a serial session with baud-rate of 9600 and the right COM-port (visible in Device Manager).
   You may need to press the RESET-button.
   
   

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   anchor Figure_VHM title-alignment center

   Figure 4: Terminal(MicroBlaze output)

2.2 Reference Design - Introduction

We provide a reference design that interacts with most of the peripheral on the module. The provided design "TE0717 TE0802 test board" shows how to connect the different parts of the module to simplify the development of your own application. You can use it for your own design but keep in mind the overall FPGA resources and power consumption before deployment.

The reference design we are introducing in this guide is "TE0717 TE0802 test board". The most important steps to get it up and running are explained on TE0717 TE0802 Test Board. The Download is available here.

The reference design is only usable with the specified Vivado/Vitis version. Always use the same version of Xilinx Software for one Project. (e.g. use reference design 2021.2.1 with vitis installation 2021.2.1)

The components of the reference design are illustrated in the following figure:

Figure 5: Blockdiagram of the Reference Design

title Block Design

Image Added

Figure 6: Vivado Address Editor - Address Mapping

For example the AXI GPIO IP Core which has a LED1 connected to it, can be controlled with software(C/C++) by raising the bits mapped to the address 0x4000 0000.

The VIO Core enables you to control connected IOs via the Vivado Hardware Manager(like LED2).

3 Notes

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