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Overview

Refer to https://wiki.trenz-electronic.de/display/PD/TE0715+TRM for online version of this manual and the rest of available documentation.

The Trenz Electronic TE0715 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z015 or XC7Z030) with 1GByte of DDR3 SDRAM, 32MBytes of SPI Flash memory, Gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips.

Key Features

• Industrial-grade Xilinx Zynq-7000 SoC (XC7Z015, XC7Z030)

• Rugged for shock and high vibration
• 2 × ARM Cortex-A9
• 10/100/1000 Mbps Ethernet transceiver PHY
• MAC address EEPROM
• 32-bit wide 1GB DDR3 SDRAM
• 32 MByte quad SPI Flash memory
• Programmable clock generator
  • Transceiver clock (default 125 MHz)
• Plug-on module with 2 × 100-pin and 1 × 60-pin high-

...

Download PDF version of this document.

Overview

Refer to https://wiki.trenz-electronic.de/display/PD/TE0715+TRM for online version of this manual and the rest of available documentation.

The Trenz Electronic TE0715 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z015 or XC7Z030) with 1GB of DDR3 SDRAM, 32MB of SPI flash memory, gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips.

Key Features

• Industrial-grade Xilinx Zynq-7000 (XC7Z015, XC7Z030) SoC

• Rugged for shock and high vibration
• 2 × ARM Cortex-A9
• 10/100/1000 Mbps Ethernet transceiver PHY
• MAC address EEPROM
• 32-Bit wide 1GB DDR3 SDRAM
• 32 MByte QSPI flash memory
• Programmable clock generator
  • Transceiver clock (default 125 MHz)
• Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
• 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on B2B connectors
• 4 GTP/GTX (high-performance transceiver) lanes
  • GTP/GTX (high-performance transceiver) clock input
• USB 2.0 high-speed ULPI transceiver
• On-board high-efficiency DC-DC converters
  • 4 .0 A x 1.0 V power rail1
  • .5 3 A x 1.5 0 V power rail1.5
  • 3 A x 1.8 2 V power rail
  • 3 A x 1.35 V power rail
  • 3 A x 1.8 V power rail
• System System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• Temperature compensated RTC (real-time clock)
• User LED
• Evenly-spread supply pins for good signal integrity

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TE0715 block diagram.

Main Components

Figure 2: TE0715 main components.

• 1. Xilinx Zynq-7000 all programmable SoC, U5
• 2. System Controller CPLD, U26
• 3. Programmable quad clock generator , U10
• 4. 10/100/1000 Mbps Ethernet PHY, U7
• 5. 2 x 4-Gbit DDR3L SDRAM (1.35 V), U12 and U13
• 6. Hi-speed USB 2.0 ULPI transceiver, U6
  
• 7a. B2B connector Samtec Razor Beam™ LSHM-150, JM1
• 7b. B2B connector Samtec Razor Beam™ LSHM-150, JM2
• 7c. B2B connector Samtec Razor Beam™ LSHM-130, JM3
• 8. 32-MByte quad SPI Flash memory, U14
• 9. Low-power RTC with battery backed SRAM, U16
• 10. 4A PowerSoC DC-DC converter, U1
• 11. Green LED (DONE), D2
• 12. Red LED (SC), D3
• 13. Green LED (MIO7), D4
• 14. 2-bit bidirectional 1-MHz I²C bus voltage-level translator, U20

...

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

By default the TE-0715 supports quad SPI and SD Card boot modes which is controlled by the MODE input signal from the B2B JM1 connector.

Table 2: Boot MODE signal description.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

I/O I/O signals connected to the SoC's I/O bank and B2B connector: 

Table 3: General overview of board to board I/O signals.

For detailed information about the pin-For detailed information about the pin out, please refer to the Pin-out Table. 

JTAG Interface

JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2. 

...

JTAG Signal

...

B2B Connector Pin

...

System Controller I/O Pins

Special purpose pins are connected to System Controller CPLD and have following default configuration:

...

No hard wired function on PCB, when forced low pulls POR_B low to

emulate power on reset.

...

Active low reset, gated to POR_B.

...

On-board LEDs

...

D2

...

Green

...

DONE

...

Reflects inverted DONE signal. ON when FPGA is not configured,

OFF as soon as PL is configured.

This LED will not operate if the SC can not power on the 3.3V output

rail that also powers the 3.3V circuitry on the module.

...

D3

...

Red

...

SC

...

D4

...

Green

...

MIO7

...

User controlled, default OFF (when PS7 has not been booted).

MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board connector connection and Zynq SoC pin connection:

Table 4: MGT lanes overview.

Below are listed MGT bank reference clock sources.

Table 5: MGT reference clock sources.

JTAG Interface

JTAG access to the Xilinx Zynq SoC is provided through B2B connector JM2. 

Table 6: JTAG interface signals.

System Controller CPLD I/O Pins

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Table 7: System Controller CPLD I/O pins.

Quad SPI Interface

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Table 8: Quad SPI interface signals and connections.

SD Card Interface

SD Card interface is connected form the Zynq SoC's PS MIO bank 501 to the B2B connector JM1, signals MIO40 .. MIO45.

Ethernet Interface

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the IN5 pin of the PLL chip (U10).

Ethernet PHY connection

Table 9: Ethernet interface.

USB Interface

USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The

Clocking

...

PS CLK

...

33.3333 MHz

...

U11

...

PS_CLK

...

PS subsystem main clock.

...

ETH PHY reference

...

25.000000 MHz

...

U9

...

-

...

USB PHY reference

...

52.000000 MHz

...

U15

...

-

...

PLL reference

...

25.000000 MHz

...

U18

...

-

...

GT REFCLK0

...

-

...

B2B

...

U9/V9

...

Externally supplied from baseboard.

...

GT REFCLK1

...

125 MHz

...

U10 Si5338

...

U5/V5

...

Default clock is 125 MHz.

Default MIO Mapping

...

Ethernet PHY LED2

INTn Signal.

...

Gigabit Ethernet

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 2552.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the IN5 pin of the PLL chip (U10).

Ethernet PHY connection

...

Can be routed via PL to any free PL I/O pin in B2B connector.

This LED is connected to PL via level-shifter implemented in

system controller CPLD.

...

By default the PHY address is strapped to 0x00, alternate

configuration is possible.

...

USB Interface

USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 52.000000 MHz oscillator (U15).

USB PHY connection

...

U15).

USB PHY connection

Table 10: USB interface.

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for host or device modes. A mini-USB connector can be used for USB device mode. A micro-USB connector can be used for device mode, OTG mode or host mode.

I2C Interface

On-board I²C devices are connected to the Zynq SoC's PS bank 501 MIO48 (SCL) and MIO49 (SDA) which is configured as I2C1 by default. As bank 501 VCC_MIO1_501 is fixed to 1.8V, there is a bi-directional voltage-level translator used to connect 3.3V I²C slave devices to the bus. Table below lists I²C slave device addresses and functions:

Table 11: Slave devices connected to the I²C interface.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U26) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.

DDR Memory

TE0715 module has up to 1 GBytes of DDR3L SDRAM arranged into 32-bit wide memory bus. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board quad SPI Flash memory S25FL256S (U14) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512. The Ethernet PHY RGMII interface is connected to the Zynq SoC's PS bank 501 pins MIO16 .. MIO27. Reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the programmable clock generator (U10) pin IN5.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U6) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq SoC's PS bank 501 pins MIO28 .. 39. Reference clock input is supplied from the on-board 52.000000 MHz oscillator (U15).

MAC Address EEPROM

A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I²C slave device address 0x50.

RTC - Real Time Clock

An temperature compensated Intersil ISL12020M is used for Real Time Clock (U16). Battery voltage must be supplied to the module from the baseboard. Battery backed registers can be accessed over I²C bus at slave address of 0x6F. General purpose RAM is at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.

Programmable Clock Generator

There is a Silicon Labs programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed via the I²C bus, slave device address is 0x70.

Table 12: Programmable clock generator I/Os.

Oscillators

The module has following reference clock signals provided by on-board oscillators:

Table 13: Reference clock signals.

On-board LEDs

Table 14: On-board LEDs

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for host or device modes. A mini-USB connector can be used for USB device mode. A micro-USB connector can be used for device mode, OTG mode or host mode.

I2C Interface

On-board I²C devices are connected to MIO48 and MIO49 which are configured as I2C1 by default. I²C addresses for on-board devices are listed in the table below:

...

PLL

...

Boot Process

By default the TE-0715 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B JM1 connector.

...

MODE Signal State

...

High or open

...

QSPI

...

Low or ground

...

SD Card

On-board Peripherals

32 MByte Quad SPI Flash Memory

On-board QSPI flash memory S25FL256S (U14) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Processing System (PS) Peripherals

...

Temperature compensated RTC.

...

Clocking

RTC - Real Time Clock

An temperature compensated Intersil ISL12020M is used for Real Time Clock (U16). Battery voltage must be supplied to the module from the baseboard. Battery backed registers can be accessed over I²C bus at slave address of 0x6F. General purpose RAM is at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.

PLL - Phase-Locked Loop

There is a Silicon Labs I²C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I²C bus address 0x70.

PLL connection

...

IN1/IN2

...

Externally supplied

...

Needs decoupling on base board.

...

IN3

...

25.000000 MHz

...

Fixed input clock.

...

IN4

...

-

...

-

...

IN5/IN6

...

125MHz

...

Ethernet PHY output clock.

...

CLK0

...

-

...

Not used, disabled.

...

CLK1

...

-

...

Not used, disabled.

...

CLK2 A/B

...

125MHz

...

MGT reference clock 1.

...

CLK3A

...

- 

...

Bank 34 clock input, default disabled, User clock.

...

CLK3B

...

-

...

Not used, disabled.

MAC Address EEPROM

A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I²C slave address 0x50.

Power and Power-On Sequence

Power

...

Consumption

Power supply with minimum current capability of 3A for system startup is recommended. Maximum power consumption of a module mainly depends on the design running on the FPGA. Xilinx provides power estimator excel sheets to calculate power consumption.

Power Consumption

It is also possible to evaluate the power consumption of the design with Vivado. See also Trenz Electronic Wiki FAQ.

 * TBD - To Be Determined soon with reference design setup.

Table 15: Typical power consumption.

Power Distribution Dependencies

Image Added

Figure 3: Module power distribution diagramLowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise due to the DC-DC converter efficiency (it decreases when VIN/VOUT ratio rises). Typical module power consumption is between 2-3W.

Power-On Sequence

Image Added

Figure 4: TE0820-02 power-on sequence diagram.

For highest efficiency of the on-board DC/-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.It is important that all baseboard I/Os are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered upup simultaneously.

See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 module.

...

Table 16: TE0715 power rails.

Bank Voltages

Board to Board Connectors

...

Variants Currently in Production

...

Temperature

Range

...

B2B Connector

Height

...

Technical Specifications

Absolute Maximum Ratings

...

Parameter

...

Units

...

Notes

...

VIN supply voltage

...

-0.3

...

6.0

...

V

...

3.3VIN supply voltage

...

-0.4

...

3.6

...

V

...

PL IO bank supply voltage for HP I/O banks (VCCO)

...

Voltage on module JTAG pins

...

-0.4

...

V

...

Storage temperature

...

-40

...

+85

...

°C

...

Recommended Operating Conditions

...

PL I/O bank supply voltage for HR

I/O banks (VCCO)

...

PL I/O bank supply voltage for HP

I/O banks (VCCO)

...

TE0715-xx-15 does not have

HP banks

...

Xilinx datasheet DS191

or DS187

...

TE0715-xx-15 does not have

HP banks

(*) Check datasheet

...

Table 17: TE0715 bank voltages.

Board to Board Connectors

Variants Currently in Production

Table 18: TE0715 variants currently in production.

Technical Specifications

Absolute Maximum Ratings

Table 19: TE0715 module absolute maximum ratings.

Recommended Operating Conditions

Table 20: TE0715 module recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial and extended grade: -40°C to +85°C.

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers

• Mating height with standard connectors: 8mm

• PCB thickness: 1.6mm

• Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers

 All dimensions are given in millimeters.

Image Added Image Added

Figure 5: TE0715 physical dimensions.

Revision History

Hardware Revision History

Table 21: TE0715 module hardware revision history.

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Image Added Image Added

Figure 6: TE0715 hardware revision number.

Document Change History

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial and extended grade: -40°C to +85°C.

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers

• Mating height with standard connectors: 8mm

• PCB thickness: 1.6mm

• Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers

 All dimensions are given in millimeters.

Image Removed Image Removed

Weight

26 g - Plain module

8.8 g - Set of bolts and nuts

Revision History

Hardware Revision History

...

Notes

...

01

...

Prototypes

...

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Image Removed Image Removed

Document Change History

Table 22: Document change history.

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