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Overview

Refer to https://wiki.trenz-electronic.de/display/PD/TE0715+TRM for online version of this manual and the rest of available documentation.

 The Trenz Electronic TE0715 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z015 or XC7Z030) with 1GByte of DDR3 SDRAM, 32MBytes of SPI Flash memory, Gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips.

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• Industrial-grade Xilinx Zynq-7000 SoC (XC7Z015, XC7Z030)

• Rugged for shock and high vibration
• 2 × ARM Cortex-A9
• 10/100/1000 Mbps Ethernet transceiver PHY
• MAC address EEPROM
• 32-bit wide 1GB DDR3 SDRAM
• 32 MByte quad SPI Flash memory
• Programmable clock generator
  • Transceiver clock (default 125 MHz)
• Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
• 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on B2B connectors
• 4 GTP/GTX (high-performance transceiver) lanes
  • GTP/GTX (high-performance transceiver) clock input
• USB 2.0 high-speed ULPI transceiver
• On-board high-efficiency DC-DC converters
  • 4 A x 1.0 V power rail
  • 3 A x 1.0 V power rail
  • 3 A x 1.2 V power rail
  • 3 5 A x 1.5 35 V power rail
  • 1.5 3 A x 1.8 V power rail
• System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• Temperature compensated RTC (real-time clock)
• User LED
• Evenly-spread supply pins for good signal integrity

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• 1. Xilinx Zynq-7000 all programmable SoC, U5
• 2. System Controller CPLD, U26
• 3. Programmable quad clock generator , U10
• 4. 10/100/1000 Mbps Ethernet PHY, U7
• 5. 2 x 4-Gbit DDR3L SDRAM (1.35 V), U12 and U13
• 6. Hi-speed USB 2.0 ULPI transceiver, U6
  
• 7a. B2B connector Samtec Razor Beam™ LSHM-150, JM1
• 7b. B2B connector Samtec Razor Beam™ LSHM-150, JM2
• 7c. B2B connector Samtec Razor Beam™ LSHM-130, JM3
• 8. 32-MByte quad SPI Flash memory, U14
• 9. Low-power RTC with battery backed SRAM, U16
• 10. 4A PowerSoC DC-DC converter, U1
• 11. Green LED (DONE), D2
• 12. Red LED (SC), D3
• 13. Green LED (MIO7), D4
• 14. 2-bit bidirectional 1-MHz I²C bus voltage-level translator, U20

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Table 3: General overview of board to board I/O signals.

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For detailed information about the pin-out, please refer to the Pin-out Table. 

MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connector connection and FPGA pins Zynq SoC pin connection:

Table 4: MGT lanes overview.

Below are listed MGT banks bank reference clock sources.

Table 5: MGT reference clock sources.

JTAG Interface

JTAG access to the Xilinx Zynq -7000 SoC is provided through B2B connector JM2. 

Table 6: MGT lanes JTAG interface signals. 

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System Controller CPLD I/O Pins

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Table 7: System Controller CPLD I/O pins.

Quad SPI Interface

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

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Table 8: Quad SPI interface signals and connections.page-break

SD Card Interface

SD Card interface is connected form the Zynq SoC's PS MIO bank 501 to the B2B connector JM1, signals MIO40 .. MIO45.

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Table 9: Ethernet interface.

USB Interface

USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 52.000000 MHz oscillator (U15).

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On-board I²C devices are connected to the Zynq SoC's PS bank 501 MIO48 (SCL) and MIO49 (SDA) which are is configured as I2C1 by default. As bank 501 VCC_MIO1_501 is fixed to 1.8V, there is a bi-directional voltage-level translator used to connect 3.3V I²C addresses for on-board devices are listed in the table belowslave devices to the bus. Table below lists I²C slave device addresses and functions:

Table 11: Slave devices connected to the I²C interface.

On-board Peripherals

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A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address , that is compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I²C slave device address 0x50.

RTC - Real Time Clock

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Table 12: Programmable clock generator I/Os.

Oscillators

The module has following reference clock signals provided by on-board oscillators:

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Power

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Consumption

Power supply with minimum current capability of 3A for system startup is recommended. Power ConsumptionMaximum power consumption of a module mainly depends on the design running on the FPGA. Xilinx provides power estimator excel sheets to calculate power consumption. It is also possible to evaluate the power consumption of the design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 15: Power Typical power consumption.

 * TBD - To Be Determined.

Power Distribution Dependencies

Image Added

Figure 3: Module power distribution diagram.Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise due to the DC-DC converter efficiency (it decreases when VIN/VOUT ratio rises). Typical module power consumption is between 2-3W.

Power-On Sequence

Image Added

Figure 4: TE0820-02 power-on sequence diagram.

For For highest efficiency of the on-board DC/-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.It is important that all baseboard I/Os are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up

See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 module.

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Board to Board Connectors

Variants Currently in Production

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Temperature

Range

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B2B Connector

Height

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Trenz shop TE0715 overview page
English page	German page

Table 18: TE0715 variants currently in production.

Technical Specifications

Absolute Maximum Ratings

Table 18: TE0715 variants currently in production.

Technical Specifications

Absolute Maximum Ratings

Table 19: TE0715 module absolute maximum ratings. 

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Recommended Operating Conditions

Table 20: TE0715 module recommended operating conditions.

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 All dimensions are given in millimeters.

Figure 35: TE0715 physical dimensions.

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Hardware Revision History

Table 21: TE0715 module hardware revision history.

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Figure 46: TE0715 hardware revision number.

Document Change History

Table 22: Document change history.

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