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Table of Contents

Table of Contents

Overview


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Refer to https://wiki.trenz-electronic.de/display/PD/TE0715+TRM for online version of this manual and the rest of available documentation.



 The Trenz Electronic TE0715 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z015 or XC7Z030) with 1GByte of DDR3 SDRAM, 32MBytes of SPI Flash memory, Gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips.

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  • Industrial-grade Xilinx Zynq-7000 SoC (XC7Z015, XC7Z030)

  • Rugged for shock and high vibration
  • 2 × ARM Cortex-A9
  • 10/100/1000 Mbps Ethernet transceiver PHY
  • MAC address EEPROM
  • 32-bit wide 1GB DDR3 SDRAM
  • 32 MByte quad SPI Flash memory
  • Programmable clock generator
    • Transceiver clock (default 125 MHz)
  • Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
  • 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on B2B connectors
  • 4 GTP/GTX (high-performance transceiver) lanes
    • GTP/GTX (high-performance transceiver) clock input
  • USB 2.0 high-speed ULPI transceiver
  • On-board high-efficiency DC-DC converters
    • 4 A x 1.0 V power rail
    • 3 A x 1.0 V power rail
    • 3 A x 1.2 V power rail
    • 3 5 A x 1.5 35 V power rail
    • 1.5 3 A x 1.8 V power rail
  • System management
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)
  • User LED
  • Evenly-spread supply pins for good signal integrity

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For detailed information about the pin-out, please refer to the Pin-out Table. 

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MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board connector connection and Zynq SoC pin connection:

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Table 4: MGT lanes overview.

 


Below are listed MGT bank reference clock sources.

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Table 5: MGT reference clock sources.

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JTAG Interface

JTAG access to the Xilinx Zynq -7000 SoC is provided through B2B connector JM2. 

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Table 6: JTAG interface signals.

 


Note
JTAGEN pin in B2B connector JM1 should be kept low or grounded for normal operation.

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System Controller CPLD I/O Pins

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Table 7: System Controller CPLD I/O pins.

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Quad SPI Interface

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

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Table 8: Quad SPI interface signals and connections.

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SD Card Interface

SD Card interface is connected form the Zynq SoC's PS MIO bank 501 to the B2B connector JM1, signals MIO40 .. MIO45.

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Table 9: Ethernet interface.

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USB Interface

USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 52.000000 MHz oscillator (U15).

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On-board I2C devices are connected to the Zynq SoC's PS bank 501 MIO48 (SCL) and MIO49 (SDA) which are is configured as I2C1 by default. I2C addresses for on-board devices are listed in the table belowAs bank 501 VCC_MIO1_501 is fixed to 1.8V, there is a bi-directional voltage-level translator used to connect 3.3V I2C slave devices to the bus. Table below lists I2C slave device addresses and functions:

RTCBattery backed RAM
I2C DeviceICI2C Slave AddressNotes
24AA025E48EEPROMU190x50 Serial EEPROMs with EUI-48™ node identity.
ISL12020MU160x6F Low-power RTC with battery backed SRAM.
ISL12020MU160x57Integrated Battery backed SRAM integrated into RTC.
SI5338AU10PLL0x70 Programmable quad clock generator.

Table 11: Slave devices connected to the I2C interface.

On-board Peripherals

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A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address , that is compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave device address 0x50.

RTC - Real Time Clock

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Table 12: Programmable clock generator I/Os.

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Oscillators

The module has following reference clock signals provided by on-board oscillators:

SourceSignalFrequencyDestinationPin NameNotes
U18CLK25.000000 MHzU10IN3 
U9CLK25.000000 MHzU7XTAL_IN 
U11

PS-CLK

33.333333 MHz

U5

PS_CLK_500

Zynq SoC PS subsystem main clock.

U15

CLK

52.000000 MHz

U6

REFCLK

USB3320C PHY reference clock.

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Warning

TE0715-xx-30 has several HP banks on B2B connectors. Those banks have maximum voltage tolerance of 1.8V. Please check special instructions for the baseboard to be used with TE0715-xx-30.

Power

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Consumption

Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

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Maximum power consumption of a module mainly depends on the design running on the FPGA. Xilinx provides power estimator excel sheets to calculate power consumption. It is also possible to evaluate the power consumption of the design with Vivado. See also Trenz Electronic Wiki FAQ.

Power Input PinTypical Current
VINTo be determined.
3.3VINTo be determined.

Table 15: Typical power consumption.

Power Distribution Dependencies

Image Added

Figure 3: Module power distribution diagram

Table 15: Power consumption.

 * TBD - To Be Determined.

Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise due to the DC-DC converter efficiency (it decreases when VIN/VOUT ratio rises). Typical module power consumption is between 2-3W.

Power-On Sequence

Image Added

Figure 4: TE0820-02 power-on sequence diagram.


For highest efficiency of the on-board DC/-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.It is important that all baseboard I/Os are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up

Warning

To avoid any damage to the module, check for stabilized on-board voltages should be carried out (3.3V (JM2-10, 12) or 1.8V(JM1-39) output) before powering up any FPGA's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 module.

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B2B Name

B2B JM1 Pins

B2B JM2 Pins

Direction

Note
VIN1, 3, 52, 4, 6, 8InputSupply voltage.
3.3VIN13, 15-InputSupply voltage.
VCCIO139, 11-InputHigh range bank voltage.
VCCIO34-5Input

TE0715-xx-15: high range bank voltage.

TE0715-xx-30: high performance bank voltage.
VCCIO35-7, 9Input

TE0715-xx-15: high range bank voltage.

TE0715-xx-30: high performance bank voltage.
VBAT_IN79-InputRTC battery-buffer supply voltage.
3.3V-10, 12OutputInternal 3.3V voltage level.
1.8V39-OutputInternal 1.8V voltage level.
DDR_PWR-19OutputInternal 1.5V or 1.35V voltage level, depends on revision.
VREF_JTAG 
91OutputJTAG reference voltage (3.3V).

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Board to Board Connectors

Include Page
4 x 5 SoM LSHM B2B Connectors
4 x 5 SoM LSHM B2B ConnectorsIN:Samtec LSHMIN:Samtec LSHM

Variants Currently in Production

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Temperature

Range

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B2B Connector

Height

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Trenz shop TE0715 overview page
English pageGerman page

Table 18: TE0715 variants currently in production.

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Notes

VIN supply voltage

-0.3

6.0

V

-

3.3VIN supply voltage

-0.4

3.6

V

-
VBAT supply voltage-16.0V-
PL IO bank supply voltage for HR I/O banks (VCCO)-0.53.6V-

PL IO bank supply voltage for HP I/O banks (VCCO)

-0.52.0VTE0715-xx-15 does not have HP banks.
I/O input voltage for HR I/O banks-0.4VCCO + 0.55V-
I/O input

Table 18: TE0715 variants currently in production.

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Notes

VIN supply voltage

-0.3

6.0

V

-

3.3VIN supply voltage

-0.4

3.6

V

-
VBAT supply voltage-16.0V-
PL IO bank supply voltage for HR I/O banks (VCCO)-0.53.6V-
PL IO bank supply voltage for HP I/O banks (VCCO)-0.5552VCCO + 0.055VTE0715-xx-15 does not have HP banks.
I/O input voltage for HR I/O banks-0.4VCCO + 0.55V-
I/O input voltage for HP I/O banks-0.55VCCO + 0.55VTE0715-xx-15 does not have HP banks.
GT receiver (RXP/RXN) GT receiver (RXP/RXN) and transmitter (TXP/TXN)-0.51.26V-

Voltage on module JTAG pins

-0.4

VCCO_0 + 0.55

V

VCCO_0 is 3.3V nominal.

Storage temperature

-40

+85

°C

-
Storage temperature without the ISL12020MIRZ and 88E1512-55+100°C-

Table 19: TE0715 module absolute maximum ratings.

 


Note
Assembly variants for higher storage temperature range are available on request.

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Recommended Operating Conditions

  
ParameterMinMaxUnitsNotesReference Document
VIN supply voltage2.55.5V  

3.3VIN supply voltage3.1353.465V  

VBAT_VBAT_IN supply voltage2.75.5V 

PL I/O bank supply voltage for HR

I/O banks (VCCO)

1.143.465V
Xilinx datasheet DS191

PL I/O bank supply voltage for HP

I/O banks (VCCO)

1.141.89V

TE0715-xx-15 does not have

HP banks

Xilinx datasheet DS191
I/O input voltage for HR I/O banks(*)(*)V(*) Check datasheet

Xilinx datasheet DS191

or DS187

I/O input voltage for HP I/O banks(*)(*)V

TE0715-xx-15 does not have

HP banks

(*) Check datasheet

Xilinx datasheet DS191
Voltage on Module JTAG pins3.1353.465VVCCO_0 is 3.3 V nominal 

Table 20: TE0715 module recommended operating conditions.

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  • Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers

  • Mating height with standard connectors: 8mm

  • PCB thickness: 1.6mm

  • Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers

 All dimensions are given in millimeters.

Image Removed Image Removed

Figure 3: TE0715 physical dimensions.

Revision History

Hardware Revision History

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Notes

...

01

...

Prototypes

...

  • thickness: 1.6mm

  • Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers

 All dimensions are given in millimeters.

Image Added Image Added

Figure 5: TE0715 physical dimensions.

Revision History

Hardware Revision History

DateRevision

Notes

Link to PCNDocumentation Link
2022-12-2105Third production release

Click to see PCN

TE0715-05
2016-06-2104Second production releaseClick to see PCNTE0715-04
-03First production release
TE0715-03
-02Prototypes
TE0715-02
-

01

Prototypes



Table 21: TE0715 module hardware revision history.

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Image Added Image Added

Figure 6: TE0715 hardware revision number.

Document Change History

Date

Revision

Contributors

Description

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • Updated Key features: DCDC current rating
  • Added revision 5 in Hardware revision history
2021-06-21v.87John Hartfiel
  • Bugfix Link to PDF download
2018-07-06v.86John Hartfiel
  • Link to shop production list
  • Change normal Bank power note to important note

2017-11-14

v.85John Hartfiel
  • Replace B2B connector section
2017-09-10v.82Jan Kumann
  • Document template revision added.
  • Revised block diagram with new I2C part.
  • Power distribution diagram added.
  • Power-on sequence diagram added.
  • Sections rearranged, some

Table 21: TE0715 module hardware revision history.

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Image Removed Image Removed

Figure 4: TE0715 hardware revision number.

Document Change History

Date

Revision

Contributors

Description

Page info
modified-datemodified-date
dateFormatyyyy-MM-dd
Jan Kumann
  • Document template revision added.
  • Sections rearranged and missing ones added.
  • Weight section removed.
2017-06-07

v.64

Jan Kumann
  • Minor formatting.
2017-03-02

v.59

Thorsten Trenz
  • Corrected boot mode table.
2017-02-10

v.58

Thorsten Trenz
  • Corrected PLL initial delivery state.
2017-01-25
v.55

 


Jan Kumann
  • New block diagram.
2017-01-14

v.50

Jan Kumann
  • Product revision 04 images added.
  • Formatting changes and small corrections.
2016-11-15

v.45

Thorsten Trenz
  • Added B2B Connector section.
2016-10-18
v.40

Ali Naseri

  • Added table "power rails".
2016-06-28
v.38

 

Thorsten Trenz, Emmanuel Vassilakis, Jan Kumann

  • New overall document layout with shorter table of contents.
  • Revision 01 PCB pictures replaced with the revision 03 ones.
  • Fixed link to Master Pin-out Table.
  • New default MIO mapping table design.
  • Revised Power-on section.
  • Added links to related Xilinx online documents.
  • Physical dimensions pictures revised.
  • Revision number picture with explanation added.
2016-04-27v.33

Thorsten Trenz, Emmanuel Vassilakis

  • Added table "Recommended Operating Conditions".
  • Storage Temperature edited.
2016-03-31v.10

Philipp Bernhardt, Antti Lukats

  • Initial version.

Table 22: Document change history.

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