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Template Revision 2.2 TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM" |
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Table of Contents
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Overview
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The Trenz Electronic TE0714 is an industrial-grade SoM (System on Module) based on Xilinx Artix-7, 16 Mbyte MByte Flash memory and powerful switching mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. All modules in 4 x 5 cm form factor are mechanically compatible.
Block Diagram
Main Components
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Top view
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- Xilinx Artix-7 FPGA, U4
- SPI Flash, U7
- B2B Connector, JM2
- B2B Connector, JM1
- MEMS Oscillator (PL Clock), U8
- Single Output Low-Dropout Linear Regulator, U6 (1.2V_MGT)
- Single Output Low-Dropout Linear Regulator, U5 (1.0V_MGT)
- Low-Jitter Precision LVDS Oscillator (GT Clock), U2
- Red Indication LED,D4
- Step-Down DC-DC Converter, U1 (1.0V)
- PFET Load Switch With Configurable Slew Rate, Q1 (3.3V)
- Low Power Step-Down DC-DC Converter, U3 (1.8V)
- Voltage Detector for Circuit Initialization and Timing Supervision, U23
Key Features
TE0714 is the smallest module with transceiver (3 x 4 cm).
Refer to http://trenz.org/te0714-info for the current online version of this manual and other available documentation.
Key Features
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Xilinx Artix-7 FPGA
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(A15T, A35T, A50T)
- Rugged for
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- shock and
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- high vibration
- 16 MByte QSPI Flash
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- memory
- Differential MEMS
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- oscillator for
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- MGT clocking
- MEMS
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- oscillator for PL
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- clocks (Optional)
- Plug-
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- on module with 2 × 100-
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- pin high-speed hermaphroditic strips
- 138
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- FPGA I/O's (Max 68
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- differential)
5 IO's (QSPI or user I/O's)
- XADC
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- analog input
- 4 GTP (
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- high-
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- performance transceiver)
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- lanes
- GT
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- reference clock inputs
- Optimized I/O and
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- power pins for good signal integrity
- On-board
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- high-
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- efficiency DC-DC
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- converters
- Power
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- supply for
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- all on-board components
- eFUSE
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- bit-
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- stream encryption (AES)
- One
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- user configurable LED
Different configurations for cost and performance optimization available upon request. Available options are:
- FPGA Type (A15T, A35T, A50T), temperature grade
- GT
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- clock frequency (or none if not implemented)
- PL
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- clock frequency and precision (or none if not implemented)
- Config and B14
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- bank Voltage: 1.8V or 3.3V
- SPI Flash type (or none if not implemented)
- LED Color (or none if not implemented)
- PUDC Pin strapping (pull high or pull down)
- GT
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- power enable pin strapping (default power enabled or disabled)
Block Diagram
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Main Components
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- Xilinx Artix-7 FPGA (XC7A series), U4
- 16 MByte SPI Flash, U7
- B2B connector Samtec Razor Beam™ LSHM-150, JM2
- B2B connector Samtec Razor Beam™ LSHM-150, JM1
- 25 MHz oscillator, U8
- Single output low-dropout linear regulator (1.2V_MGT), U6
- Single output low-dropout linear regulator (1.0V_MGT), U5
- Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
- Red indication LED, D4
- Step-down DC-DC converter (1.0V), U1
- PFET load switch with configurable slew rate (3.3V), Q1
- Low-power step-down DC-DC converter (1.8V), U3
- Voltage detector for circuit initialization and timing supervision, U23
Initial Delivery State
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Signals, Interfaces and Pins
JTAG Interface
JTAG access to the Xilinx Artix-7 device is provided through connector JM1.
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Signal Name
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B2B Pin
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Clocking
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Clock
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Default Frequency
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IC
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FPGA
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Notes
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25 MHz
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U8
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T14
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125MHz
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U2
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B6/B5
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Frequency depends on the module variant
Boot Modes
Boot mode is controlled by the MODE signal on the board to board (B2B) connector:
Control Signals
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Boot process is controlled by signals on the board to board (B2B) connector.
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MODE signal State
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SPI |
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FPGA pins D02 and |
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D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register. |
Signals, Interfaces and Pins
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JTAG Interface
JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1.
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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Please refer to the Pin-out tables page for additional information.
On-board Peripherals
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Quad SPI Flash
On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant. |
On-board LED
There is one LED on TE0714 module:.
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Clock
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Power and Power-On Sequence
To power-up a module, power supply with minimum current capability of 1A is recommended.
Power Suppy
TE0714 needs one single power supply with nominal of 3.3V.
Power Consumption
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Actual power consumption depends on the FPGA design and ambient temperature.
Power Distribution Dependencies
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Power-On Sequence
There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.
Bank Voltages
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Bank
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Voltage
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0 Config and B14
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1.8V or 3.3V
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15
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User
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Supplied from baseboard via B2B connector, max 3.3V
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34
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User
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Variants Currently In Production
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FPGA Chip Model
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B14/Config Voltage [V]
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LED
D4
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Bank Voltages
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Board to Board Connectors
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Technical Specifications
Absolute Maximum Ratings
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On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module. |
Technical Specifications
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Recommended Operating Conditions
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Recommended Operating Conditions
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This TRM is generic for all variants. Variants of modules are described here: Article Number Information Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.
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| Please check Xilinx datasheet DS181 for complete list of absolute maximum and recommended operating ratings for the Artix-7. |
Physical Dimensions
Module size: 40 mm × 30 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.
All dimensions are shown in mm. Additional sketches, drawings and schematics can be found here.
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Operating Temperature Ranges
Commercial grade modules
All parts are at least commercial temperature range of 0 °C to +70 °C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Industrial grade modules
All parts are at least industrial temperature range of -40 °C to +85 °C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Weight
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Revision History
Hardware Revision History
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Variants Currently In Production
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On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module. |
Revision History
Hardware Revision History
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Changes
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Current Hardware Revision, no changes
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Hardware revision number is printed on the PCB board next to the module model number separated by the dash.
Document Change History
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Disclaimer
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Disclaimer
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Overview
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