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Important General Note: |
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Table of Contents |
Overview
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The Trenz Electronic TE0714 is an industrial-grade SoM (System om on Module) based on Xilinx Artix-7, 16 megabyte MByte Flash memory and powerful switch-switching mode power supplies for all on-board voltages. A large number of configurable I/Os O's is provided via rugged high-speed stacking strips. All modules in 4 x 5 cm form factor are mechanically compatible.
Block diagram
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Board Components
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Top view | Bottom view |
Main Components:
Artix-7 FPGA
B2B-Connectors
- SPI Flash
- LVDS Oscillator
- Power Supply for all on-board components
Key Features
TE0714 is the smallest module with transceiver (3 x 4 cm).
Refer to http://trenz.org/te0714-info for the current online version of this manual and other available documentation.
Key Features
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Notes : - List of key features of the PCB
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(A15T, A35T, A50T)
- Rugged for shock and high vibration
- 16 MByte QSPI Flash memory
- Differential MEMS oscillator for MGT clocking
- MEMS oscillator for PL clocks (Optional)
- Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
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- GT reference clock inputs
- Optimized I/O and power pins for good signal integrity
- On-board high-efficiency DC-DC converters
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- Power supply for all on-board components
- eFUSE bit-stream encryption
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- (AES)
- One user configurable LED
Different configurations for cost and
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performance optimization available upon request.
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Available options are:
- FPGA Type (A15T, A35T, A50T), temperature grade
- GT
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- clock frequency (or none if not
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- clock frequency and precision (or none if not
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- implemented)
- Config and B14
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- bank Voltage: 1.8V or 3.3V
- SPI Flash type (or none if not
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- implemented)
- LED Color (or none if not
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- implemented)
- PUDC Pin strapping (pull high or pull down)
- GT
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- power enable pin strapping (default power enabled or disabled)
Block Diagram
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Main Components
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Current Assembly Variants
Variant | FPGA | GT Clock | PL Clock | PUDC | GT PWR Enable | B14/Config Voltage | SPI Flash | LED |
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Standard | A35T-2I | 125MHz | 25Mhz | HIGH | Enabled | 3.3V | S25FL127S | Red |
35-2IC6 | A35T-2I | 125MHz | 25MHz | HIGH | Enabled | 1.8V | N25Q128 | Red |
Signals, Interfaces and Pins
Boot Modes
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- Add List below
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- Xilinx Artix-7 FPGA (XC7A series), U4
- 16 MByte SPI Flash, U7
- B2B connector Samtec Razor Beam™ LSHM-150, JM2
- B2B connector Samtec Razor Beam™ LSHM-150, JM1
- 25 MHz oscillator, U8
- Single output low-dropout linear regulator (1.2V_MGT), U6
- Single output low-dropout linear regulator (1.0V_MGT), U5
- Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
- Red indication LED, D4
- Step-down DC-DC converter (1.0V), U1
- PFET load switch with configurable slew rate (3.3V), Q1
- Low-power step-down DC-DC converter (1.8V), U3
- Voltage detector for circuit initialization and timing supervision, U23
Initial Delivery State
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Storage device name | Content | Notes |
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SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor | SPI Flash Quad Enable bit | Programmed |
| SPI Flash main array | demo design |
| eFUSE USER | Not programmed |
| eFUSE Security | Not programmed |
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Control Signals
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- Overview of Boot Mode, Reset, Enables,
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Boot process is controlled by signals on the board to board (B2B) connector
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Signal | Direction | Signal State | Description |
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BOOTMODE
| input |
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MODE signal
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| high or open | Master SPI, x4 Mode
| low or ground
| Slave SelectMAP | PROG_B | input | pulsed low | Clear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge). | DONE | output | high | Completion of configuration sequence. |
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SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register. |
Signals, Interfaces and Pins
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Notes : - For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
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JTAG Interface
JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1.
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title | JTAG signals. |
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Signal Name | B2B Pin |
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TCK | JM1:89 | TDI | JM1:85 | TDO | JM1:87 | TMS | JM1:91 |
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Clocking
Clock | Frequency | IC | FPGA | Notes |
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CLK | 25 MHz | U8, SiT8008 | | |
MGT_CLK | | | | |
Peripherals
LED's
There is 1 LED on TE0714:
LED | Color | Connected to | Notes |
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D4 | green | pin K18 | |
Power
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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14 | JM1 | 6 | VCCIO_0 |
| 14 | JM2 | 36 | VCCIO_0 | NB! 17 LVDS pairs possible. | 15 | JM2 | 48 | VCCIO15 | Supplied by the baseboard. | 34 | JM1 | 48 | VCCIO34 | Supplied by the baseboard. | 216 | JM1 | 16 | MGT_AVCC MGT_AVTT | 4 x GTP lanes. |
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Please refer to the Pin-out tables page for additional information.
On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Ethernet PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Quad SPI Flash
On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant. |
On-board LED
There is one LED on TE0714 module.
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LED | Color | FPGA | Notes |
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D4 | Red | K18 | User programmable |
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Clock
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Clock | Default Frequency | IC | FPGA | Notes |
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CLK25MHz | 25 MHz | U8 | T14 | Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank. | MGT_CLK | 125MHz | U2 | B6/B5 | Frequency depends on the module variant |
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Power and Power-On Sequence
To power-up a module, For startup, a power supply with minimum current capability of 1A is recommended.
TE0714 needs one single power supply with nominal of 3.3V.
Power Consumption
Power Supplies
Vin | 3.3 V | Typical 200 mA, depending on customer design and connections |
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Test Condition (25 °C ambient) | VIN Current mA | Notes |
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TE0714-35, TEBT0714, empty design, GT not enabled | 110mA |
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Actual power consumption depends on the FPGA design and ambient temperature.
Power Distribution Dependencies
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Power-On Sequence
There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.
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Power Rails
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| | | Direction | Note |
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VIN | 98, 100 | - | input | supply voltage | VCCIO_0 | - | 54 | input | high range bank voltage | VCCIO_15 | - | 53 | input | high range bank voltage | VCCIO_34 | 62 | - | input | high range bank voltage | 3.3V | 84 | - | output | internal 3.3V voltage level | 1.8V | - | 17 | output | internal 1.8V voltage level |
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Bank Voltages
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0 Config and B14 | 1.8V or 3.3V | Depends on module assembly variant. See R21, R22 and R27 assembly option* | 15 | User |
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Supplied from baseboard via B2B connector, max 3.3V | 34 | User |
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Initial Delivery state
Storage device name | Content | Notes |
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SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash Quad Enable bit | Programmed | |
SPI Flash main array | demo design | |
EFUSE USER | Not programmed | |
EFUSE Security | Not programmed | |
Hardware Revision History
Revision | Changes |
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01 | Current Hardware Revision, no changes |
Technical Specification
Supplied from baseboard via B2B connector, max 3.3V |
- *R21 assembled: 3.3V and B2B is output if R27 is assembled
- *R22 assembled 1.8V and B2B is output if R27 is assembled
- *R21 and R22 not assembled , B2B is input and carrier defines voltage → pay attention on assembled flash!
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Board to Board Connectors
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- This section is optional and only for modules.
- use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors
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Include Page |
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| 3 x 4 SoM LSHM B2B Connectors |
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| 3 x 4 SoM LSHM B2B Connectors |
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Technical Specifications
Absolute Maximum Ratings
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- | HR I/O banks supply voltage (VCCO) | -0.5 | 3.6 | V |
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Xilinx datasheet DS181 | HR I/O banks input voltage |
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GTP transceivers Tx/Rx input voltage | -0.5 | 1.26 | V |
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Xilinx datasheet DS181 | Voltage on |
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module JTAG pins | -0.4 | VCCO_0 + 0.55 | V |
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Xilinx datasheet DS181 | Storage |
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C
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Storage Temperature without the LXDC2HL18A-052
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-40
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+125
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C
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Recommended Operating Conditions
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This TRM is generic for all variants. Variants of modules are described here: Article Number Information Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables. Scroll Table Layout |
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- | HR I/O banks supply voltage (VCCO) | 1.14 | 3.465 | V |
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Xilinx datasheet DS181 | HR I/O banks input voltage |
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Xilinx datasheet DS181 | Voltage on |
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0 | VCCO_0 + 5% | V | Xilinx datasheet DS181 |
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Please check Xilinx Datasheet for complete list of Absolute maximum and recommended operating ratings for the Artix-7 device (DS181). |
Physical Dimensions
Module size: 40 mm × 30 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approx. approximately 2.5 mm. Please download the step model for exact numbers.
All dimensions are shown in mm. Additional sketches, drawings and schematics can be found here.
Temperature Ranges
Commercial grade modules
All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Industrial grade modules
All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Weight
Variant | Weight g | Note |
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2IC6 | 8.3 | Plain Module |
Document Change History
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Date
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Revision
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Authors
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Description
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2016-06-01
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Disclaimer
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Image Added Image Added |
Variants Currently In Production
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On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module. |
Revision History
Hardware Revision History
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Hardware revision number is printed on the PCB board next to the module model number separated by the dash.
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Document Change History
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Date | Revision | Authors | Description |
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prefix | v. |
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| Page info |
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infoType | Modified by |
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| - Updated storage temperatur.
| 2021-04-07 | v59 | Thomas Steffens | - changed operating conditions
| 2019-03-04 | v55 | John Hartfiel | - Restore and modify v.50
- Correction max IO count on key features
- Change history table
- typo correction
| 2019-01-07 | v.50 | John Hartfiel | - Updated to TRM version 2.2
- Style modifications
| | v.48 | Martin Rohrmüller | - Updated to TRM version 2.1
- Updated B2B Connectors
- Style modifications
| 2018-09-17 | v.38 | Martin Rohrmüller | - Added power rail section
- Added Rev 02 Flash PCN
- Corrected table headings
| 2018-09-17 | v.36 | Martin Rohrmüller | | 2018-04-04 | | Martin Rohrmüller | Corrected clock net designator in table. | 2017-05-28 | | Jan Kumann | - Board-to-Board I/O section added.
- New physical dimensions images.
- Documents sections rearranged.
| 2017-03-20 | | John Hartfiel | - Notes on Clocking section.
| 2017-01-27 | v.25 | Jan Kumann | | 2016-12-01 | | Jan Kumann | - Changes in the document structure, few corrections.
| 2016-11-18 | v.14
| Thorsten Trenz, Emmanuel Vassilakis | - Hardware revision 02 specific changes.
| 2016-06-01 | | | | -- | all | Page info |
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Disclaimer
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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