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Template Revision 2.0 - on construction2 TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM" |
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Table of Contents
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Overview
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The Trenz Electronic TE0714 is an industrial-grade SoM (System on Module) based on Xilinx Artix-7, 16 MByte Flash memory and powerful switching mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. TE0714 is the smallest module with transceiver (3 x 4 cm).
Refer to http://trenz.org/te0714-info for the current online version of this manual and other available documentation.
Key Features
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Xilinx Artix-7 FPGA (A15T, A35T, A50T)
- Rugged for shock and high vibration
- 16 MByte QSPI Flash memory
- Differential MEMS oscillator for MGT clocking
- MEMS oscillator for PL clocks (Optional)
- Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
- 144 FPGA I/O's (Max 68 differential)
- XADC analog input
- 4 GTP (high-performance transceiver) lanes
- GT reference clock inputs
- Optimized I/O and power pins for good signal integrity
- On-board high-efficiency DC-DC converters
- Power supply for all on-board components
- eFUSE bit-stream encryption (AES)
- One user configurable LED
Different configurations for cost and performance optimization available upon request. Available options are:
- FPGA Type (A15T, A35T, A50T), temperature grade
- GT clock frequency (or none if not implemented)
- PL clock frequency and precision (or none if not implemented)
- Config and B14 bank Voltage: 1.8V or 3.3V
- SPI Flash type (or none if not implemented)
- LED Color (or none if not implemented)
- PUDC Pin strapping (pull high or pull down)
- GT power enable pin strapping (default power enabled or disabled)
Block Diagram
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title | Figure 1: TE0714 block diagram |
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Table of Contents
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Overview
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The Trenz Electronic TE0714 is an industrial-grade SoM (System on Module) based on Xilinx Artix-7, 16 MByte Flash memory and powerful switching mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. TE0714 is the smallest module with transceiver (3 x 4 cm).
Refer to http://trenz.org/te0714-info for the current online version of this manual and other available documentation.
Key Features
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Xilinx Artix-7 FPGA (A15T, A35T, A50T)
- Rugged for shock and high vibration
- 16 MByte QSPI Flash memory
- Differential MEMS oscillator for MGT clocking
- MEMS oscillator for PL clocks (Optional)
- Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
- 138 FPGA I/O's (Max 68 differential)
5 IO's (QSPI or user I/O's)
- XADC analog input
- 4 GTP (high-performance transceiver) lanes
- GT reference clock inputs
- Optimized I/O and power pins for good signal integrity
- On-board high-efficiency DC-DC converters
- Power supply for all on-board components
- eFUSE bit-stream encryption (AES)
- One user configurable LED
Different configurations for cost and performance optimization available upon request. Available options are:
- FPGA Type (A15T, A35T, A50T), temperature grade
- GT clock frequency (or none if not implemented)
- PL clock frequency and precision (or none if not implemented)
- Config and B14 bank Voltage: 1.8V or 3.3V
- SPI Flash type (or none if not implemented)
- LED Color (or none if not implemented)
- PUDC Pin strapping (pull high or pull down)
- GT power enable pin strapping (default power enabled or disabled)
Block Diagram
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Main Components
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- Xilinx Artix-7 FPGA (XC7A series), U4
- 16 MByte SPI Flash, U7
- B2B connector Samtec Razor Beam™ LSHM-150, JM2
- B2B connector Samtec Razor Beam™ LSHM-150, JM1
- 25 MHz oscillator, U8
- Single output low-dropout linear regulator (1.2V_MGT), U6
- Single output low-dropout linear regulator (1.0V_MGT), U5
- Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
- Red indication LED, D4
- Step-down DC-DC converter (1.0V), U1
- PFET load switch with configurable slew rate (3.3V), Q1
- Low-power step-down DC-DC converter (1.8V), U3
- Voltage detector for circuit initialization and timing supervision, U23
Main Components
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- Xilinx Artix-7 FPGA (XC7A series), U4
- 16 MByte SPI Flash, U7
- B2B connector Samtec Razor Beam™ LSHM-150, JM2
- B2B connector Samtec Razor Beam™ LSHM-150, JM1
- 25 MHz oscillator, U8
- Single output low-dropout linear regulator (1.2V_MGT), U6
- Single output low-dropout linear regulator (1.0V_MGT), U5
- Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
- Red indication LED, D4
- Step-down DC-DC converter (1.0V), U1
- PFET load switch with configurable slew rate (3.3V), Q1
- Low-power step-down DC-DC converter (1.8V), U3
- Voltage detector for circuit initialization and timing supervision, U23
Initial Delivery State
Initial Delivery State
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title | Table 1: Initial delivery state of programmable devices on the module. |
Storage device name
Content
Notes
SPI Flash OTP Area
Empty, not programmed
Except serial number programmed by flash vendor
SPI Flash Quad Enable bit
Programmed
SPI Flash main array
demo design
eFUSE USER
Not programmed
eFUSE Security
Not programmed
Control Signals
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Direction | Signal State | BOOTMODEDescription input | high or open Master SPI, x4 Mode low or ground Slave SelectMAP PROG_B | input | pulsed low | Clear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge). | DONE | output | high | Completion of configuration sequence. | |
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SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register. |
Signals, Interfaces and Pins
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JTAG Interface
JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1.
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title | Table 3: JTAG signals. |
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Control Signals
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JM1:91
On-board LED's
There is one LED on TE0714 module:
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title | Table 4: LED connection. |
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LED
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Color
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FPGA
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Notes
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D4
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Red
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K18
Clock
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title | Table 5: Clock signals. |
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Clock
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Default Frequency
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IC
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FPGA
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Notes
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25 MHz
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U8
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T14
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125MHz
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U2
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B6/B5
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Frequency depends on the module variant
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SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register. |
Signals, Interfaces and Pins
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JTAG Interface
JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1.
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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FPGA Bank
I/O Signal Count | Voltage Level | Notes | 14 | JM1 | 6 | VCCIO_0 | 14 | JM2 | 36 | VCCIO_0 | NB! 17 LVDS pairs possible. | 15 | JM2 | 48 | VCCIO15 | Supplied by the baseboard. | 34 | JM1 | 48 | VCCIO34 | Supplied by the baseboard. | 216 | JM1 | 16 | MGT_AVCC MGT_AVTT 4 x GTP lanes. | |
Please refer to the Pin-out tables page for additional information.
On-board Peripherals
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16 MByte Quad SPI Flash
On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant. |
Power and Power-On Sequence
To power-up a module, power supply with minimum current capability of 1A is recommended.
TE0714 needs one single power supply with nominal of 3.3V.
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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Please refer to the Pin-out tables page for additional information.
On-board Peripherals
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Quad SPI Flash
On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant. |
On-board LED
There is one LED on TE0714 module.
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Power and Power-On Sequence
To power-up a module, power supply with minimum current capability of 1A is recommended.
TE0714 needs one single power supply with nominal of 3.3V.
Power Consumption
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Actual power consumption depends on the FPGA design and ambient temperature.
Power Distribution Dependencies
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Power-On Sequence
There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.
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Test Condition (25 °C ambient) | VIN Current mA | Notes | TE0714-35, TEBT0714, empty design, GT not enabled | 110mA |
Actual power consumption depends on the FPGA design and ambient temperature.
Power Distribution Dependencies
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title | Figure 3: Power Distribution |
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Bank Voltages
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Power-On Sequence
There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.
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Voltages on B2B- Connector B2B JM1-Pin B2B JM1-Pin Direction | Note | | |||||||||||||||||||
VIN | 98, 100 | - | input | supply voltage | |||||||||||||||||
VCCIO_0 | - | 54 | input | high range bank voltage | |||||||||||||||||
VCCIO_15 | - | 53 | input | high range bank voltage | |||||||||||||||||
VCCIO_34 | 62 | - | input | high range bank voltage | |||||||||||||||||
3.3V | 84 | - | output | internal 3.3V voltage level | |||||||||||||||||
1.8V | - | 17 | output | internal 1.8V voltage level |
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Board to Board Connectors
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Technical Specifications
Absolute Maximum Ratings
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15 | User | Supplied from baseboard via B2B connector, max 3.3V | |||||||||||||||||
34 | User | Supplied from baseboard via B2B connector, max 3.3V |
Board to Board Connectors
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Recommended Operating Conditions
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This TRM is generic for all variants. Variants of modules are described here: Article Number Information Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.
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Physical Dimensions
Module size: 40 mm × 30 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.
All dimensions are shown in mm. Additional sketches, drawings and schematics can be found here.
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Variants Currently In Production
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Technical Specifications
Absolute Maximum Ratings
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title | Table 10: Module absolute maximum ratings. |
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VIN supply voltage
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-0.1
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6.0
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V
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Voltage on module JTAG pins
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-0.4
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V
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Storage temperature
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-40
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+85
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°C
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Recommended Operating Conditions
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title | Table 11: Recommended Operating Conditions |
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Physical Dimensions
Module size: 40 mm × 30 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.
All dimensions are shown in mm. Additional sketches, drawings and schematics can be found here.
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Weight
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2IC6 | 8.3 | Plain Module |
Variants Currently In Production
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Set correct link to the shop page overview table of the product on English and German, if not available, set
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On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module. |
Revision History
Hardware Revision History
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https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/
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Trenz shop TE0714 overview page | ||||||||||||||||
English page | German page |
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On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module. |
Revision History
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Hardware revision number is printed on the PCB board next to the module model number separated by the dash.
Document Change History
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2018-11-01 | 02 | Replace obsolete SPI Flash | in preparation | TE0714-02 | ||||||||||||
2016-08-04 | 02 | VCCIO0 added to B2B | PCN-20160815 | TE0714-02 | 01 | - | - | TE0714-01 |
Hardware revision number is printed on the PCB board next to the module model number separated by the dash.
Document Change History
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2016-06-01
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v.9
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Antti Lukats
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Disclaimer
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Disclaimer
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Refer to https://wiki.trenz-electronic.de/display/PD/TE0713+TRM for online version of this manual and the rest of available documentation.