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Template Revision 2.0 - on construction2 TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM" |
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Important General Note: |
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anchor | Figure_OV_BD |
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title | Figure 1: TE0714 block diagram |
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tbstyle | top |
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diagramWidth | 641 |
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revision | 4 |
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Main Components
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anchor | Figure_OV_MC |
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title | Figure 2: TE0714 main components |
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- Xilinx Artix-7 FPGA (XC7A series), U4
- 16 MByte SPI Flash, U7
- B2B connector Samtec Razor Beam™ LSHM-150, JM2
- B2B connector Samtec Razor Beam™ LSHM-150, JM1
- 25 MHz oscillator, U8
- Single output low-dropout linear regulator (1.2V_MGT), U6
- Single output low-dropout linear regulator (1.0V_MGT), U5
- Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
- Red indication LED, D4
- Step-down DC-DC converter (1.0V), U1
- PFET load switch with configurable slew rate (3.3V), Q1
- Low-power step-down DC-DC converter (1.8V), U3
- Voltage detector for circuit initialization and timing supervision, U23
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Initial Delivery State
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anchor | Table_InitialOV_Delivery_StateIDS |
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title | Table 1: Initial delivery state of programmable devices on the module. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style |
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widths | 30%,25%,45% | widths |
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sortEnabled | false |
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Storage device name | Content | Notes |
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SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor | SPI Flash Quad Enable bit | Programmed |
| SPI Flash main array | demo design |
| eFUSE USER | Not programmed |
| eFUSE Security | Not programmed |
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Control Signals
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- Overview of Boot Mode, Reset, Enables,
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Boot process is controlled by signals on the board to board (B2B) connector.
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anchor | Table_BootOV_SignalsBS |
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title | Table 2: Boot signals. |
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orientation | portrait |
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Signal | Direction | Signal State | Description |
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BOOTMODE
| input | high or open | Master SPI, x4 Mode
| low or ground
| Slave SelectMAP | PROG_B | input | pulsed low | Clear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge). | DONE | output | high | Completion of configuration sequence. |
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Note |
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SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register. |
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JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1.
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anchor | Table_SIP_JTAG |
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title | Table 3: JTAG signals. |
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Signal Name | B2B Pin |
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TCK | JM1:89 | TDI | JM1:85 | TDO | JM1:87 | TMS | JM1:91 |
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On-board LED
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:There is one LED on TE0714 module.
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anchor | Table_SIP_LEDsB2B |
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title | Table 4: LED connection.B2B I/Os |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style | widths |
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cellHighlighting | true |
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LED | Color | FPGA | Notes |
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D4 | Red | K18 | User programmable |
Clock
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anchor | Table_Clocks |
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title | Table 5: Clock signals. |
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cellHighlighting | true |
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FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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14 | JM1 | 6 | VCCIO_0 |
| 14 | JM2 | 36 | VCCIO_0 | NB! 17 LVDS pairs possible. | 15 | JM2 | 48 | VCCIO15 | Supplied by the baseboard. | 34 | JM1 | 48 | VCCIO34 | Supplied by the baseboard. | 216 | JM1 | 16 | MGT_AVCC MGT_AVTT | 4 x GTP lanes. |
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Please refer to the Pin-out tables page for additional information.
On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Ethernet PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Quad SPI Flash
On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant. |
On-board LED
There is one LED on TE0714 module.
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Clock
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Default Frequency
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IC
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FPGA
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Notes
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25 MHz
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U8
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T14
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125MHz
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U2
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B6/B5
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Frequency depends on the module variant
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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anchor | Table_B2BOBP_LEDs |
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title | Table 6: B2B I/OsLED connection. |
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orientation | portrait |
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FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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14 | JM1 | 6 | VCCIO_0 | 14 | JM2 | 36 | VCCIO_0 | NB! 17 LVDS pairs possible. |
15 | JM2 | 48 | VCCIO15 | Supplied by the baseboard. |
34 | JM1 | 48 | VCCIO34 | Supplied by the baseboard. |
216 | JM1 | 16 | MGT_AVCC MGT_AVTT | 4 x GTP lanes. |
Please refer to the Pin-out tables page for additional information.
On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Ethernet PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Quad SPI Flash
On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.
Note |
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant. |
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sortEnabled | false |
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LED | Color | FPGA | Notes |
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D4 | Red | K18 | User programmable |
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Clock
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anchor | Table_OBP_Clocks |
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title | Clock signals. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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widths | 14%,15%,6%,9%,56% |
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cellHighlighting | true |
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Clock | Default Frequency | IC | FPGA | Notes |
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CLK25MHz | 25 MHz | U8 | T14 | Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank. | MGT_CLK | 125MHz | U2 | B6/B5 | Frequency depends on the module variant |
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Power and Power-On Sequence
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Power Consumption
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anchor | Table_PowerPWR_ConsumptionPC |
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title | Table 7: Power Consumption |
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Test Condition (25 °C ambient) | VIN Current mA | Notes |
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TE0714-35, TEBT0714, empty design, GT not enabled | 110mA |
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Power Distribution Dependencies
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anchor | Figure_PWR_PD |
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title | Figure 3: Power Distribution |
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revisionfitWindow | 6false |
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diagramName | PD-TE0714 |
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simpleViewer | true |
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width | links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 641 |
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revision | 10 |
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Power-On Sequence
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anchor | Figure_PowerPWR_SequencyPS |
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title | Figure 4: Power-On Sequency |
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border | false |
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tbstyle | top |
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lbox | true |
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diagramWidth | 641 |
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Power Rails
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anchor | Table_PWR_Power_RailsPR |
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title | Table 8: Power Rails |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style |
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widths | sortByColumn | 1 |
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| | | Direction | Note |
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VIN | 98, 100 | - | input | supply voltage | VCCIO_0 | - | 54 | input | high range bank voltage | VCCIO_15 | - | 53 | input | high range bank voltage | VCCIO_34 | 62 | - | input | high range bank voltage | 3.3V | 84 | - | output | internal 3.3V voltage level | 1.8V | - | 17 | output | internal 1.8V voltage level |
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Bank Voltages
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anchor | Table_BankPWR_VoltagesBV |
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title | Table 9: Bank Voltages |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | stylewidths | default |
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0 Config and B14 | 1.8V or 3.3V | Depends on module assembly variant. See R21, R22 and R27 assembly option* | 15 | User | Supplied from baseboard via B2B connector, max 3.3V | 34 | User | Supplied from baseboard via B2B connector, max 3.3V3.3V |
- *R21 assembled: 3.3V and B2B is output if R27 is assembled
- *R22 assembled 1.8V and B2B is output if R27 is assembled
- *R21 and R22 not assembled , B2B is input and carrier defines voltage → pay attention on assembled flash!
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Board to Board Connectors
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Absolute Maximum Ratings
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anchor | Table_AbsoluteTS_Maximum_RatingsAMR |
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title | Table 10: Module absolute maximum ratings. |
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orientation | portrait |
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Parameter | Min | Max | Units | Reference Document |
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VIN supply voltage | -0.1 | 6.0 | V | - | HR I/O banks supply voltage (VCCO) | -0.5 | 3.6 | V | Xilinx datasheet DS181 | HR I/O banks input voltage | -0.4 | VCCO + 0.55 | V | Xilinx datasheet DS181 | GTP transceivers Tx/Rx input voltage | -0.5 | 1.26 | V | Xilinx datasheet DS181 | Voltage on module JTAG pins | -0.4 | VCCO_0 + 0.55 | V | Xilinx datasheet DS181 | Storage temperature | -40 | +85 | °C | - |
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Recommended Operating Conditions
.4 | VCCO_0 + 0.55 | V | Xilinx datasheet DS181 | Storage temperature | -40 | +100 | °C | - |
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Recommended Operating Conditions
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anchor | Table_TS_ROC |
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title | Recommended Operating Conditions |
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This TRM is generic for all variants. Variants of modules are described here: Article Number Information Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables. |
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anchor | Table_Recommended_Operating_Conditions |
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title | Table 11: Recommended Operating Conditions Scroll Table Layout |
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orientation | portrait |
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Parameter | Min | Max | Units | Reference Document |
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VIN supply voltage | 3.135 | 3.45 | V | - | HR I/O banks supply voltage (VCCO) | 1.14 | 3.465 | V | Xilinx datasheet DS181 | HR I/O banks input voltage | -0.20 | VCCO + 0.2020V | V | Xilinx datasheet DS181 | Voltage on module JTAG pins | 3.135 | 0 | VCCO_0 + 5%3.465 | V | Xilinx datasheet DS181 |
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Physical Dimensions
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anchor | Figure_PhysicalTS_DimensionsPD |
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title | Figure 5: Physical dimensions drawing |
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anchor | Table_TEVCP_Shop_OverviewSO |
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title | Table 12: Trenz Electronic Shop Overview |
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Hardware Revision History
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anchor | Table_HardwareRH_Revision_HistoryHRH |
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title | Table 13: Hardware Revision History |
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Document Change History
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anchor | Table_DocumentRH_Change_HistoryDCH |
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title | Table 14: Document change history |
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orientation | portrait |
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Date | Revision | Authors | Description | Page info |
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modified-date | modified-date |
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dateFormat | yyyy-MM-dd |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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infoType | Modified by |
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type | Flat |
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showVersions | false | Authors | Description | Page info |
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dateFormat | yyyy-MM-dd |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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infoType | Modified by |
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type | Flat |
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| - Updated storage temperatur.
| 2021-04-07 | v59 | Thomas Steffens | - changed operating conditions
| 2019-03-04 | v55 | John Hartfiel | - Restore and modify v.50
- Correction max IO count on key features
- Change history table
- typo correction
| 2019-01-07 | v.50 | John Hartfiel | - Updated to TRM version 2.2
- Style modifications
| | v.48 | Martin Rohrmüller | - Updated to TRM version 2.1
- Updated B2B Connectors
- Style modifications
| 2018-09-17 | Vv.38 | Martin Rohrmüller | - Added power rail section
- Added Rev 02 Flash PCN
- Corrected table headings
| 2018-09-17 | v.36 | Martin Rohrmüller | | 2018-04-04 | | Martin Rohrmüller | Corrected clock net designator in table. | 2017-05-28 | V | Jan Kumann | - Board-to-Board I/O section added.
- New physical dimensions images.
- Documents sections rearranged.
| 2017-03-20 | V | John Hartfiel | - Notes on Clocking section.
| 2017-01-27 | v.25 | Jan Kumann | | 2016-12-01 | | Jan Kumann | - Changes in the document structure, few corrections.
| 2016-11-18 | v.14
| Thorsten Trenz, Emmanuel Vassilakis | - Hardware revision 02 specific changes.
| 2016-06-01 | | | | -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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Disclaimer
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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