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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

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        12



      • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

        • <type>_<main section>_<name>

          • type: Figure, Table
          • main section:
            • "OV" for Overview
            • "SIP" for Signal Interfaces and Pins,
            • "OBP" for On board Peripherals,
            • "PWR" for Power and Power-On Sequence,
            • "B2B" for Board to Board Connector,
            • "TS" for Technical Specification
            • "VCP" for Variants Currently in Production
            •  "RH" for Revision History
          • name: custom, some fix names, see below
        • Fix names:
          • "Figure_OV_BD" for Block Diagram

          • "Figure_OV_MC" for Main Components

          • "Table_OV_IDS" for Initial Delivery State

          • "Table_PWR_PC" for Power Consumption

          • "Figure_PWR_PD" for Power Distribution
          • "Figure_PWR_PS" for Power Sequence
          • "Figure_PWR_PM" for Power Monitoring
          • "Table_PWR_PR" for Power Rails
          • "Table_PWR_BV" for Bank Voltages
          • "Table_TS_AMR" for Absolute_Maximum_Ratings

          • "Table_TS_ROC" for Recommended_Operating_Conditions

          • "Figure_TS_PD" for Physical_Dimensions
          • "Table_VCP_SO" for TE_Shop_Overview
          • "Table_RH_HRH" for Hardware_Revision_History

          • "Table_RH_DCH" for Document_Change_History
      • Use Anchor in the document: add link macro and add "#<anchorname>
      • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>
  • ...

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  • Xilinx Artix-7 FPGA (A15T, A35T, A50T)

  • Rugged for shock and high vibration
  • 16 MByte QSPI Flash memory
  • Differential MEMS oscillator for MGT clocking
  • MEMS oscillator for PL clocks (Optional)
  • Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
    • 144 138 FPGA I/O's (Max 68 differential)
    • 5 IO's (QSPI or user I/O's)

    • XADC analog input
    • 4 GTP (high-performance transceiver) lanes
    • GT reference clock inputs
    • Optimized I/O and power pins for good signal integrity
  • On-board high-efficiency DC-DC converters
  • Power supply for all on-board components
  • eFUSE bit-stream encryption (AES)
  • One user configurable LED

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Scroll Title
anchorFigure_OV_BD
titleTE0714 block diagram


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Main Components

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titleTE0714 main components


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  1. Xilinx Artix-7 FPGA (XC7A series), U4
  2. 16 MByte SPI Flash, U7
  3. B2B connector Samtec Razor Beam™ LSHM-150, JM2
  4. B2B connector Samtec Razor Beam™ LSHM-150, JM1
  5. 25 MHz oscillator, U8
  6. Single output low-dropout linear regulator (1.2V_MGT), U6
  7. Single output low-dropout linear regulator (1.0V_MGT), U5
  8. Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
  9. Red indication LED, D4
  10. Step-down DC-DC converter (1.0V), U1
  11. PFET load switch with configurable slew rate (3.3V), Q1
  12. Low-power step-down DC-DC converter (1.8V), U3
  13. Voltage detector for circuit initialization and timing supervision, U23 

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Initial Delivery State

Scroll Title
anchorTable_OV_IDS
titleInitial delivery state of programmable devices on the module.

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Storage device name

Content

Notes

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor

SPI Flash Quad Enable bit

Programmed


SPI Flash main array

demo design


eFUSE USER

Not programmed


eFUSE Security

Not programmed




Control Signals

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  • Overview of Boot Mode, Reset, Enables,
Boot process is controlled by signals on the board to board (B2B) connector.
Scroll Title
anchorTable_OV_BS
titleBoot signals.

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SignalDirection

Signal State

Description

BOOTMODE


input

high or open

Master SPI, x4 Mode

low or ground

Slave SelectMAP

PROG_Binputpulsed lowClear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge).
DONEoutputhighCompletion of configuration sequence.



Note

SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register.


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Scroll Title
anchorTable_SIP_JTAG
titleJTAG signals.

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Signal Name

B2B Pin

TCKJM1:89
TDIJM1:85
TDOJM1:87
TMS

JM1:91


...

Scroll Title
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titleB2B I/Os

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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
14JM16VCCIO_0
14JM236VCCIO_0NB! 17 LVDS pairs possible.
15JM248VCCIO15Supplied by the baseboard.
34JM148VCCIO34Supplied by the baseboard.
216JM116

MGT_AVCC

MGT_AVTT

4 x GTP lanes.


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titleLED connection.

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LED

Color

FPGA

Notes

D4

Red

K18

User programmable


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Scroll Title
anchorTable_OBP_Clocks
titleClock signals.

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Clock

Default Frequency

IC

FPGA

Notes

CLK25MHz

25 MHz

U8

T14

Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank.
MGT_CLK

125MHz

U2

B6/B5

Frequency depends on the module variant


...

Scroll Title
anchorTable_PWR_PC
titlePower Consumption

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Test Condition (25 °C ambient)VIN Current mANotes
TE0714-35, TEBT0714, empty design, GT not enabled110mA


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titlePower Distribution


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Power-On Sequence

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titlePower-On Sequency


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Power Rails

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titlePower Rails

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Voltages on B2B-

Connector

B2B JM1-Pin

B2B JM1JM2-Pin

DirectionNote
VIN98, 100-inputsupply voltage
VCCIO_0-54inputhigh range bank voltage
VCCIO_15-53inputhigh range bank voltage
VCCIO_3462-inputhigh range bank voltage
3.3V84-outputinternal 3.3V voltage level
1.8V-17outputinternal 1.8V voltage level


...

Scroll Title
anchorTable_PWR_BV
titleBank Voltages

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Bank

Voltage

Notes

0 Config and B14

1.8V or 3.3V

Depends on module assembly variant. See R21, R22 and R27 assembly option*

15

User

Supplied from baseboard via B2B connector, max 3.3V

34

User

Supplied from baseboard via B2B connector, max 3.3V

Board to Board Connectors

  • *R21 assembled: 3.3V and B2B is output if R27 is assembled
  • *R22 assembled 1.8V and B2B is output if R27 is assembled
  • *R21 and R22 not assembled , B2B is input and carrier defines voltage → pay attention on assembled flash!

Board to Board Connectors

Page properties
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  • This section is optional and only for modules.
  • use "include page" macro and link to the
Page properties
hiddentrue
idComments
  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

...

Scroll Title
anchorTable_TS_AMR
titleModule absolute maximum ratings.

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ParameterMinMaxUnitsReference Document

VIN supply voltage

-0.1

6.0

V

-
HR I/O banks supply voltage (VCCO)-0.53.6VXilinx datasheet DS181
HR I/O banks input voltage-0.4VCCO + 0.55VXilinx datasheet DS181
GTP transceivers Tx/Rx input voltage-0.51.26VXilinx datasheet DS181

Voltage on module JTAG pins

-0.4

VCCO_0 + 0.55

V

Xilinx datasheet DS181

Storage temperature

-40

+85100

°C

-


Recommended Operating Conditions

scroll-title
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Recommended Operating Conditions

Table_TS_ROC
titleRecommended Operating Conditions
Scroll Title
anchorTable_TS_ROC
titleRecommended Operating Conditions

This TRM is generic for all variants.

Variants of modules are described here: Article Number Information

Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C

Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C

Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C

The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

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ParameterMinMaxUnitsReference Document
VIN supply voltage3.1353.45V-
HR I/O banks supply voltage (VCCO)1.143.465VXilinx datasheet DS181
HR I/O banks input voltage-0.20VCCO + 0.2020VVXilinx datasheet DS181
Voltage on module JTAG pins3.1350VCCO_0 + 5%3.465VXilinx datasheet DS181


Physical Dimensions

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Scroll Title
anchorTable_VCP_SO
titleTrenz Electronic Shop Overview

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Trenz shop TE0714 overview page
English pageGerman page


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Scroll Title
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titleHardware Revision History

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DateRevisionPCNDocumentation LinkNote
2016-08-0402PCN-20160815TE0714-02VCCIO0 added to B2B

01

-TE0714-01

-


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Scroll Title
anchorTable_RH_DCH
titleDocument change history

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Sept 2018

Date

Revision

Authors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

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infoTypeCurrent version
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  • Updated storage temperatur.
2021-04-07v59Thomas Steffens
  • changed operating conditions
2019-03-04v55John Hartfiel
  • Restore and modify v.50
  • Correction max IO count on key features
  • Change history table
  • typo correction
2019-01-07v.50John Hartfiel
  • Updated to TRM version 2.2
  • Style modifications

2018-09-19

v.48Martin Rohrmüller
  • Updated to TRM version 2.1
  • Updated B2B Connectors
  • Style modifications
2018-09-17

v.38

Martin Rohrmüller
  • Added power rail section
  • Added Rev 02 Flash PCN
  • Corrected table headings
2018-09-17v.36Martin Rohrmüller
  • Update to TRM version 2.0 with DrawIO Figures

  • Added Figure Power Distribution
2018-04-04

v.35

Martin RohrmüllerCorrected clock net designator in table.
2017-05-28

v.27

Jan Kumann
  • Board-to-Board I/O section added.
  • New physical dimensions images.
  • Documents sections rearranged.
2017-03-20

v.26

John Hartfiel
  • Notes on Clocking section.
2017-01-27v.25Jan Kumann
  • New block diagram.
2016-12-01

v.17

Jan Kumann
  • Changes in the document structure, few corrections.
2016-11-18
v.14

Thorsten Trenz, Emmanuel Vassilakis

  • Hardware revision 02 specific changes.

2016-06-01

v.9

Antti Lukats

  • Initial version.
--all

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