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Important General Note: |
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anchor | Figure_OV_BD |
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title | TE0714 block diagram |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false | diagramDisplayName |
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lbox | true |
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revision | 4 |
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diagramName | BD-TE0714-02 |
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simpleViewer | true | width |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 641 |
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revision | 4 |
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Main Components
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anchor | Figure_OV_MC |
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title | TE0714 main components |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false | diagramDisplayName |
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lbox | true |
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revision | 2 |
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diagramName | MC-TE0714 |
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simpleViewer | true | width |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 641 |
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revision | 2 |
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- Xilinx Artix-7 FPGA (XC7A series), U4
- 16 MByte SPI Flash, U7
- B2B connector Samtec Razor Beam™ LSHM-150, JM2
- B2B connector Samtec Razor Beam™ LSHM-150, JM1
- 25 MHz oscillator, U8
- Single output low-dropout linear regulator (1.2V_MGT), U6
- Single output low-dropout linear regulator (1.0V_MGT), U5
- Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
- Red indication LED, D4
- Step-down DC-DC converter (1.0V), U1
- PFET load switch with configurable slew rate (3.3V), Q1
- Low-power step-down DC-DC converter (1.8V), U3
- Voltage detector for circuit initialization and timing supervision, U23
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Initial Delivery State
Scroll Title |
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style |
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widths | 30%,25%,45% |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor | SPI Flash Quad Enable bit | Programmed |
| SPI Flash main array | demo design |
| eFUSE USER | Not programmed |
| eFUSE Security | Not programmed |
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Control Signals
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- Overview of Boot Mode, Reset, Enables,
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Boot process is controlled by signals on the board to board (B2B) connector.
Scroll Title |
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anchor | Table_OV_BS |
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title | Boot signals. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style |
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widths | 16%,14%,19%,51 |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Signal | Direction | Signal State | Description |
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BOOTMODE
| input | high or open | Master SPI, x4 Mode
| low or ground
| Slave SelectMAP | PROG_B | input | pulsed low | Clear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge). | DONE | output | high | Completion of configuration sequence. |
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Note |
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SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register. |
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Scroll Title |
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anchor | Table_SIP_JTAG |
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title | JTAG signals. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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stylesortByColumnwidths | 1 |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Signal Name | B2B Pin |
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TCK | JM1:89 | TDI | JM1:85 | TDO | JM1:87 | TMS | JM1:91 |
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Scroll Title |
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anchor | Table_SIP_B2B |
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title | B2B I/Os |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style |
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widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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14 | JM1 | 6 | VCCIO_0 |
| 14 | JM2 | 36 | VCCIO_0 | NB! 17 LVDS pairs possible. | 15 | JM2 | 48 | VCCIO15 | Supplied by the baseboard. | 34 | JM1 | 48 | VCCIO34 | Supplied by the baseboard. | 216 | JM1 | 16 | MGT_AVCC MGT_AVTT | 4 x GTP lanes. |
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Scroll Title |
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anchor | Table_OBP_LEDs |
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title | LED connection. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style |
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widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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LED | Color | FPGA | Notes |
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D4 | Red | K18 | User programmable |
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Scroll Title |
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anchor | Table_OBP_Clocks |
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title | Clock signals. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style |
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widths | 14%,15%,6%,9%,56% |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Clock | Default Frequency | IC | FPGA | Notes |
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CLK25MHz | 25 MHz | U8 | T14 | Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank. | MGT_CLK | 125MHz | U2 | B6/B5 | Frequency depends on the module variant |
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Scroll Title |
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anchor | Table_PWR_PC |
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title | Power Consumption |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style | widths |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Test Condition (25 °C ambient) | VIN Current mA | Notes |
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TE0714-35, TEBT0714, empty design, GT not enabled | 110mA |
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false | diagramDisplayName |
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lbox | true |
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revision | 6 |
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diagramName | PD-TE0714 |
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simpleViewer | true | width |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 641 |
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revision | 10 |
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Power-On Sequence
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Scroll Title |
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anchor | Figure_PWR_PS |
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title | Power-On Sequency |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false | diagramDisplayName |
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lbox | true |
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revision | 2 |
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diagramName | TE0714-02_Power_Sequenz |
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simpleViewer | true | width |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 641 |
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revision | 2 |
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Scroll Only |
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Power Rails
Scroll Title |
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anchor | Table_PWR_PR |
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title | Power Rails |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style |
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widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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| | | Direction | Note |
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VIN | 98, 100 | - | input | supply voltage | VCCIO_0 | - | 54 | input | high range bank voltage | VCCIO_15 | - | 53 | input | high range bank voltage | VCCIO_34 | 62 | - | input | high range bank voltage | 3.3V | 84 | - | output | internal 3.3V voltage level | 1.8V | - | 17 | output | internal 1.8V voltage level |
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Scroll Title |
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anchor | Table_PWR_BV |
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title | Bank Voltages |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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stylesortByColumnwidths | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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0 Config and B14 | 1.8V or 3.3V | Depends on module assembly variant. See R21, R22 and R27 assembly option* | 15 | User | Supplied from baseboard via B2B connector, max 3.3V | 34 | User | Supplied from baseboard via B2B connector, max 3.3V |
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Board to Board Connectors
- *R21 assembled: 3.3V and B2B is output if R27 is assembled
- *R22 assembled 1.8V and B2B is output if R27 is assembled
- *R21 and R22 not assembled , B2B is input and carrier defines voltage → pay attention on assembled flash!
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Board to Board Connectors
Page properties |
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- This section is optional and only for modules.
- use "include page" macro and link to the
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Page properties |
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- This section is optional and only for modules.
- use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors
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Scroll Title |
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anchor | Table_TS_AMR |
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title | Module absolute maximum ratings. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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stylesortByColumn | widths | sortByColumn1 | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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VIN supply voltage | -0.1 | 6.0 | V | - | HR I/O banks supply voltage (VCCO) | -0.5 | 3.6 | V | Xilinx datasheet DS181 | HR I/O banks input voltage | -0.4 | VCCO + 0.55 | V | Xilinx datasheet DS181 | GTP transceivers Tx/Rx input voltage | -0.5 | 1.26 | V | Xilinx datasheet DS181 | Voltage on module JTAG pins | -0.4 | VCCO_0 + 0.55 | V | Xilinx datasheet DS181 | Storage temperature | -40 | +85100 | °C | - |
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Recommended Operating Conditions
Recommended Operating Conditions
Table_TS_ROC | title | Recommended Operating Conditions |
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Scroll Title |
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anchor | Table_TS_ROC |
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title | Recommended Operating Conditions |
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This TRM is generic for all variants. Variants of modules are described here: Article Number Information Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables. |
Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style |
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widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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VIN supply voltage | 3.135 | 3.45 | V | - | HR I/O banks supply voltage (VCCO) | 1.14 | 3.465 | V | Xilinx datasheet DS181 | HR I/O banks input voltage | -0.20 | VCCO + 0.2020V | V | Xilinx datasheet DS181 | Voltage on module JTAG pins | 3.135 | 0 | VCCO_0 + 5%3.465 | V | Xilinx datasheet DS181 |
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Physical Dimensions
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Scroll Title |
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anchor | Table_VCP_SO |
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title | Trenz Electronic Shop Overview |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style | widths |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Scroll Title |
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anchor | Table_RH_HRH |
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title | Hardware Revision History |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | stylewidths | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Scroll Title |
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anchor | Table_RH_DCH |
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title | Document change history |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style |
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widths | sortByColumn | 1 |
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cellHighlighting | true |
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Date | Revision | Authors | Description |
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Page info |
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| modified-date |
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| modified-date |
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dateFormat | yyyy-MM-dd |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| | Flat | showVersions | false |
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Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| | - Updated storage temperatur.
| 2021-04-07 | v59 | Thomas Steffens | - changed operating conditions
| 2019-03-04 | v55 | John Hartfiel | - Restore and modify v.50
- Correction max IO count on key features
- Change history table
- typo correction
| 2019-01-07 | v.50 | John Hartfiel | - Updated to TRM version 2.2
- Style modifications
| | Sept 2018 | v.48 | Martin Rohrmüller | - Updated to TRM version 2.1
- Updated B2B Connectors
- Style modifications
| 2018-09-17 | v.38 | Martin Rohrmüller | - Added power rail section
- Added Rev 02 Flash PCN
- Corrected table headings
| 2018-09-17 | v.36 | Martin Rohrmüller | | 2018-04-04 | | Martin Rohrmüller | Corrected clock net designator in table. | 2017-05-28 | | Jan Kumann | - Board-to-Board I/O section added.
- New physical dimensions images.
- Documents sections rearranged.
| 2017-03-20 | | John Hartfiel | - Notes on Clocking section.
| 2017-01-27 | v.25 | Jan Kumann | | 2016-12-01 | | Jan Kumann | - Changes in the document structure, few corrections.
| 2016-11-18 | v.14
| Thorsten Trenz, Emmanuel Vassilakis | - Hardware revision 02 specific changes.
| 2016-06-01 | | | | -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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Disclaimer
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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