Page History

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Template Revision 2.2

TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM"

HTML

<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, use

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
Scroll Title
anchor Table_x
title Table x: Text
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default
sortByColumn 1
sortEnabled false
cellHighlighting true
Example Comment
1 2
The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>

...

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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL): for example:https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0703/

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Table of Contents

Table of Contents

Overview

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

The Trenz Electronic TE0714 is an industrial-grade SoM (System on Module) based on Xilinx Artix-7, 16 MByte Flash memory and powerful switching mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. TE0714 is the smallest module with transceiver (3 x 4 cm).

Refer to http://trenz.org/te0714-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

List of key features of the PCB

Xilinx Artix-7 FPGA (A15T, A35T, A50T)
Rugged for shock and high vibration
16 MByte QSPI Flash memory
Differential MEMS oscillator for MGT clocking
MEMS oscillator for PL clocks (Optional)
Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
- 138 FPGA I/O's (Max 68 differential)
- 5 IO's (QSPI or user I/O's)
- XADC analog input
- 4 GTP (high-performance transceiver) lanes
- GT reference clock inputs
- Optimized I/O and power pins for good signal integrity
On-board high-efficiency DC-DC converters
Power supply for all on-board components
eFUSE bit-stream encryption (AES)
One user configurable LED

Different configurations for cost and performance optimization available upon request. Available options are:

FPGA Type (A15T, A35T, A50T), temperature grade
GT clock frequency (or none if not implemented)
PL clock frequency and precision (or none if not implemented)
Config and B14 bank Voltage: 1.8V or 3.3V
SPI Flash type (or none if not implemented)
LED Color (or none if not implemented)
PUDC Pin strapping (pull high or pull down)
GT power enable pin strapping (default power enabled or disabled)

Block Diagram

Scroll Title

anchor	Figure_OV_BD
title	TE0714 block diagram

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Main Components

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Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

Scroll Title

anchor	Figure_OV_MC
title	TE0714 main components

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Xilinx Artix-7 FPGA (XC7A series), U4
16 MByte SPI Flash, U7
B2B connector Samtec Razor Beam™ LSHM-150, JM2
B2B connector Samtec Razor Beam™ LSHM-150, JM1
25 MHz oscillator, U8
Single output low-dropout linear regulator (1.2V_MGT), U6
Single output low-dropout linear regulator (1.0V_MGT), U5
Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
Red indication LED, D4
Step-down DC-DC converter (1.0V), U1
PFET load switch with configurable slew rate (3.3V), Q1
Low-power step-down DC-DC converter (1.8V), U3
Voltage detector for circuit initialization and timing supervision, U23

Initial Delivery State

Scroll Title

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title	Initial delivery state of programmable devices on the module.

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cellHighlighting	true

Storage device name	Content	Notes
SPI Flash OTP Area	Empty, not programmed	Except serial number programmed by flash vendor
SPI Flash Quad Enable bit	Programmed
SPI Flash main array	demo design
eFUSE USER	Not programmed
eFUSE Security	Not programmed

Control Signals

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Overview of Boot Mode, Reset, Enables,

Boot process is controlled by signals on the board to board (B2B) connector.

Scroll Title

anchor	Table_OV_BS
title	Boot signals.

Scroll Table Layout

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sortDirection	ASC
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Signal	Direction	Signal State	Description
BOOTMODE	input	high or open	Master SPI, x4 Mode
BOOTMODE	input	low or ground	Slave SelectMAP
PROG_B	input	pulsed low	Clear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge).
DONE	output	high	Completion of configuration sequence.

Note
SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register.

Signals, Interfaces and Pins

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Notes :

For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
- JTAG
- UART
- I2C
- MGT
- ...

JTAG Interface

JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1.

Scroll Title

anchor	Table_SIP_JTAG
title	JTAG signals.

Scroll Table Layout

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Signal Name	B2B Pin
TCK	JM1:89
TDI	JM1:85
TDO	JM1:87
TMS	JM1:91

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

Scroll Title

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FPGA Bank	B2B Connector	I/O Signal Count	Voltage Level	Notes
14	JM1	6	VCCIO_0
14	JM2	36	VCCIO_0	NB! 17 LVDS pairs possible.
15	JM2	48	VCCIO15	Supplied by the baseboard.
34	JM1	48	VCCIO34	Supplied by the baseboard.
216	JM1	16	MGT_AVCC MGT_AVTT	4 x GTP lanes.

Please refer to the Pin-out tables page for additional information.

On-board Peripherals

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Notes :

add subsection for every component which is important for design, for example:
- Ethernet PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

Quad SPI Flash

On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.

Note
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant.

On-board LED

There is one LED on TE0714 module.

Scroll Title

anchor	Table_OBP_LEDs
title	LED connection.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
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cellHighlighting	true

LED	Color	FPGA	Notes
D4	Red	K18	User programmable

Clock

Scroll Title

anchor	Table_OBP_Clocks
title	Clock signals.

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Clock	Default Frequency	IC	FPGA	Notes
CLK25MHz	25 MHz	U8	T14	Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank.
MGT_CLK	125MHz	U2	B6/B5	Frequency depends on the module variant

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

TE0714 needs one single power supply with nominal of 3.3V.

Power Consumption

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anchor	Table_PWR_PC
title	Power Consumption

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Test Condition (25 °C ambient)	VIN Current mA	Notes
TE0714-35, TEBT0714, empty design, GT not enabled	110mA

Actual power consumption depends on the FPGA design and ambient temperature.

Power Distribution Dependencies

Scroll Title

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title	Power Distribution

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Power-On Sequence

There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.

Scroll Title

anchor	Figure_PWR_PS
title	Power-On Sequency

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Power Rails

Scroll Title

anchor	Table_PWR_PR
title	Power Rails

Scroll Table Layout

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Voltages on B2B- Connector	B2B JM1-Pin	B2B JM2-Pin	Direction	Note
VIN	98, 100	-	input	supply voltage
VCCIO_0	-	54	input	high range bank voltage
VCCIO_15	-	53	input	high range bank voltage
VCCIO_34	62	-	input	high range bank voltage
3.3V	84	-	output	internal 3.3V voltage level
1.8V	-	17	output	internal 1.8V voltage level

Bank Voltages

Scroll Title

anchor	Table_PWR_BV
title	Bank Voltages

Scroll Table Layout

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cellHighlighting	true

Bank	Voltage	Notes
0 Config and B14	1.8V or 3.3V	Depends on module assembly variant. See R21, R22 and R27 assembly option*
15	User	Supplied from baseboard via B2B connector, max 3.3V
34	User	Supplied from baseboard via B2B connector, max 3.3V

*R21 assembled: 3.3V and B2B is output if R27 is assembled
*R22 assembled 1.8V and B2B is output if R27 is assembled
*R21 and R22 not assembled , B2B is input and carrier defines voltage → pay attention on assembled flash!

Board to Board Connectors

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This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

Include Page

	3 x 4 SoM LSHM B2B Connectors
	3 x 4 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

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anchor	Table_TS_AMR
title	Module absolute maximum ratings.

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Parameter	Min	Max	Units	Reference Document
VIN supply voltage	-0.1	6.0	V	-
HR I/O banks supply voltage (VCCO)	-0.5	3.6	V	Xilinx datasheet DS181
HR I/O banks input voltage	-0.4	VCCO + 0.55	V	Xilinx datasheet DS181
GTP transceivers Tx/Rx input voltage	-0.5	1.26	V	Xilinx datasheet DS181
Voltage on module JTAG pins	-0.4	VCCO_0 + 0.55	V	Xilinx datasheet DS181
Storage temperature	-40	+100	°C	-

Recommended Operating Conditions

Scroll Title

anchor	Table_TS_ROC
title	Recommended Operating Conditions

This TRM is generic for all variants.

Variants of modules are described here: Article Number Information

Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C

Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C

Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C

The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Parameter	Min	Max	Units	Reference Document
VIN supply voltage	3.135	3.45	V	-
HR I/O banks supply voltage (VCCO)	1.14	3.465	V	Xilinx datasheet DS181
HR I/O banks input voltage	-0.20	VCCO + 0.20V	V	Xilinx datasheet DS181
Voltage on module JTAG pins	0	VCCO_0 + 5%	V	Xilinx datasheet DS181

Physical Dimensions

Module size: 40 mm × 30 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.

All dimensions are shown in mm. Additional sketches, drawings and schematics can be found here.

Scroll Title

anchor	Figure_TS_PD
title	Physical dimensions drawing

Image Added

Variants Currently In Production

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id	Comments

Set correct link to the shop page overview table of the product on English and German, if not available, set
- https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/
- https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/

Scroll Title

anchor	Table_VCP_SO
title	Trenz Electronic Shop Overview

Scroll Table Layout

orientation	portrait
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repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Trenz shop TE0714 overview page
English page	German page

Note
On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module.

Revision History

Hardware Revision History

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anchor	Table_RH_HRH
title	Hardware Revision History

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Date	Revision	PCN	Documentation Link	Note
2016-08-04	02	PCN-20160815	TE0714-02	VCCIO0 added to B2B
	01	-	TE0714-01	-

Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

Image Added

Document Change History

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anchor	Table_RH_DCH
title	Document change history

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repeatTableHeaders	default
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Date

Revision

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

infoType	Current version
prefix	v.
type	Flat
showVersions	false

Page info

infoType	Modified by
type	Flat
showVersions	false

Updated storage temperatur.

2021-04-07

v59

Thomas Steffens

changed operating conditions

2019-03-04

v55

John Hartfiel

Restore and modify v.50
Correction max IO count on key features
Change history table
typo correction

2019-01-07

v.50

John Hartfiel

Updated to TRM version 2.2
Style modifications

2018-09-19

v.48

Martin Rohrmüller

Updated to TRM version 2.1
Updated B2B Connectors
Style modifications

2018-09-17

v.38

Martin Rohrmüller

Added power rail section
Added Rev 02 Flash PCN
Corrected table headings

2018-09-17

v.36

Martin Rohrmüller

Update to TRM version 2.0 with DrawIO Figures
Added Figure Power Distribution

2018-04-04

v.35

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Download PDF version of this document.

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Table of Contents

Table of Contents

Overview

The Trenz Electronic TE0714 is an industrial-grade SoM (System on Module) based on Xilinx Artix-7, 16 MByte Flash memory and powerful switching mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. TE0714 is the smallest module with transceiver (3 x 4 cm).

Refer to http://trenz.org/te0714-info for the current online version of this manual and other available documentation.

Key Features

Xilinx Artix-7 FPGA (A15T, A35T, A50T)
Rugged for shock and high vibration
16 MByte QSPI Flash memory
Differential MEMS oscillator for MGT clocking
MEMS oscillator for PL clocks (Optional)
Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
- 138 FPGA I/O's (Max 68 differential)
- 5 IO's (QSPI or user I/O's)
- XADC analog input
- 4 GTP (high-performance transceiver) lanes
- GT reference clock inputs
- Optimized I/O and power pins for good signal integrity
On-board high-efficiency DC-DC converters
Power supply for all on-board components
eFUSE bit-stream encryption (AES)
One user configurable LED

Different configurations for cost and performance optimization available upon request. Available options are:

FPGA Type (A15T, A35T, A50T), temperature grade
GT clock frequency (or none if not implemented)
PL clock frequency and precision (or none if not implemented)
Config and B14 bank Voltage: 1.8V or 3.3V
SPI Flash type (or none if not implemented)
LED Color (or none if not implemented)
PUDC Pin strapping (pull high or pull down)
GT power enable pin strapping (default power enabled or disabled)

Block Diagram

Image Removed

Page break

Main Components

Image Removed Image Removed

Xilinx Artix-7 FPGA (XC7A series), U4
16 MByte SPI Flash, U7
B2B connector Samtec Razor Beam™ LSHM-150, JM2
B2B connector Samtec Razor Beam™ LSHM-150, JM1
25 MHz oscillator, U8
Single output low-dropout linear regulator (1.2V_MGT), U6
Single output low-dropout linear regulator (1.0V_MGT), U5
Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
Red indication LED, D4
Step-down DC-DC converter (1.0V), U1
PFET load switch with configurable slew rate (3.3V), Q1
Low-power step-down DC-DC converter (1.8V), U3
Voltage detector for circuit initialization and timing supervision, U23

Initial Delivery State

...

Storage device name

...

Content

...

Notes

...

SPI Flash OTP Area

...

Empty, not programmed

...

Except serial number programmed by flash vendor

...

SPI Flash Quad Enable bit

...

Programmed

...

SPI Flash main array

...

demo design

...

eFUSE USER

...

Not programmed

...

eFUSE Security

...

Not programmed

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

...

MGT_AVCC

MGT_AVTT

...

Please refer to the Pin-out tables page for additional information.

JTAG Interface

JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1.

...

Signal Name

...

B2B Pin

...

On-board LED's

There is one LED on TE0714 module:

...

LED

...

Color

...

FPGA

...

Notes

...

D4

...

Red

...

K18

Page break

Clocking

...

Clock

...

Default Frequency

...

IC

...

FPGA

...

Notes

...

25 MHz

...

U8

...

T14

...

125MHz

...

U2

...

B6/B5

...

Frequency depends on the module variant

Boot Process

Boot mode is controlled by the MODE signal on the board to board (B2B) connector:

...

MODE signal State

...

Boot Mode

...

high or open

...

Master SPI, x4 Mode

...

low or ground

...

Slave SelectMAP

Note
SPI D2 and D3 have no pull-ups on the module so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register.

On-board Peripherals

16 MByte Quad SPI Flash

On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.

Note
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant.

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

Power Supply

TE0714 needs one single power supply with nominal of 3.3V.

Power Consumption

...

Actual power consumption depends on the FPGA design and ambient temperature.

Power-On Sequence

There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.

Bank Voltages

...

Bank

...

Voltage

...

Notes

...

0 Config and B14

...

1.8V or 3.3V

...

15

...

User

...

Supplied from baseboard via B2B connector, max 3.3V

...

34

...

User

...

Board to Board Connectors

...

Variants Currently In Production

...

anchor	Table_VCP_SO
title	Trenz Electronic Shop Overview

...

FPGA Chip Model

...

B14/Config Voltage [V]

...

Note
On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module.

Technical Specifications

Absolute Maximum Ratings

...

Parameter

...

Units

...

VIN supply voltage

...

-0.1

...

6.0

...

V

...

Voltage on module JTAG pins

...

-0.4

...

V

...

Storage temperature

...

-40

...

+85

...

°C

...

Recommended Operating Conditions

...

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Note
Please check Xilinx datasheet DS181 for complete list of absolute maximum and recommended operating ratings for the Artix-7.

Page break

Physical Dimensions

Module size: 40 mm × 30 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.

All dimensions are shown in mm. Additional sketches, drawings and schematics can be found here.

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Revision History

Hardware Revision History

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Notes

...

01

...

-

...

Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

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Document Change History

Scroll Title

anchor	Table_dch
title	Document change history.

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portrait

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ASC

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default

style

widths

2*,*,3*,4*

sortByColumn

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Date	Revision	Contributor	Description
Page info
modified-date	modified-date
dateFormat	yyyy-MM-dd

Page info

infoType	Current version
dateFormat	yyyy-MM-dd
prefix	v.
type	Flat

Page info

infoType	Modified by
dateFormat	yyyy-MM-dd
type	Flat

Correction max IO count on key features
Add new change history table
Add new product table

2019-01-09v.36

Martin RohrmüllerCorrected clock net designator in table.2017-05-28

v.27

Jan Kumann

Board-to-Board I/O section added.
New physical dimensions images.
Documents sections rearranged.

2017-03-20V

v.26

John Hartfiel

Notes on Clocking section.

2017-01-27v.25Jan Kumann

New block diagram.

2016-12-01

v.17

Jan Kumann

Changes in the document structure, few corrections.

2016-11-18

v.14

Thorsten Trenz, Emmanuel Vassilakis

Hardware revision 02 specific changes.

2016-06-01

v.9

Antti Lukats

Initial version.

--all

Page info

infoType	Modified users

dateFormatyyyy-MM-dd

type	Flat
showVersions	false

typeFlat

--

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 53

New Version Current

Key

Overview

Key Features

Block Diagram

Main Components

Initial Delivery State

Control Signals

Signals, Interfaces and Pins

JTAG Interface

Board to Board (B2B) I/Os

On-board Peripherals

Quad SPI Flash

On-board LED

Clock

Power and Power-On Sequence

Power Consumption

Power Distribution Dependencies

Power-On Sequence

Power Rails

Bank Voltages

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

Variants Currently In Production

Revision History

Hardware Revision History

Document Change History

Overview

Key Features

Block Diagram

Main Components

Initial Delivery State

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

JTAG Interface

On-board LED's

Clocking

Boot Process

On-board Peripherals

16 MByte Quad SPI Flash

Power and Power-On Sequence

Power Supply

Power Consumption

Power-On Sequence

Bank Voltages

Board to Board Connectors

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Operating Temperature Ranges

Physical Dimensions

Revision History

Hardware Revision History

Document Change History

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