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  • Xilinx Artix-7 FPGA (A15T, A35T, A50T)

  • Rugged for shock and high vibration
  • 16 MByte QSPI Flash memory
  • Differential MEMS oscillator for MGT clocking
  • MEMS oscillator for PL clocks (Optional)
  • Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
    • 144 138 FPGA I/O's (Max 68 differential)

    • 5 IO's (QSPI or user I/O's)

    • XADC analog input
    • 4 GTP (high-performance transceiver) lanes
    • GT reference clock inputs
    • Optimized I/O and power pins for good signal integrity
  • On-board high-efficiency DC-DC converters
  • Power supply for all on-board components
  • eFUSE bit-stream encryption (AES)
  • One user configurable LED

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Scroll Title
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titlePower Distribution


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Power-On Sequence

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titlePower Rails

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Voltages on B2B-

Connector

B2B JM1-Pin

B2B JM1JM2-Pin

DirectionNote
VIN98, 100-inputsupply voltage
VCCIO_0-54inputhigh range bank voltage
VCCIO_15-53inputhigh range bank voltage
VCCIO_3462-inputhigh range bank voltage
3.3V84-outputinternal 3.3V voltage level
1.8V-17outputinternal 1.8V voltage level


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Scroll Title
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titleBank Voltages

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Bank

Voltage

Notes

0 Config and B14

1.8V or 3.3V

Depends on module assembly variant. See R21, R22 and R27 assembly option*

15

User

Supplied from baseboard via B2B connector, max 3.3V

34

User

Supplied from baseboard via B2B connector, max 3.3V

Board to Board Connectors

  • *R21 assembled: 3.3V and B2B is output if R27 is assembled
  • *R22 assembled 1.8V and B2B is output if R27 is assembled
  • *R21 and R22 not assembled , B2B is input and carrier defines voltage → pay attention on assembled flash!

Board to Board Connectors

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  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

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titleModule absolute maximum ratings.

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ParameterMinMaxUnitsReference Document

VIN supply voltage

-0.1

6.0

V

-
HR I/O banks supply voltage (VCCO)-0.53.6VXilinx datasheet DS181
HR I/O banks input voltage-0.4VCCO + 0.55VXilinx datasheet DS181
GTP transceivers Tx/Rx input voltage-0.51.26VXilinx datasheet DS181

Voltage on module JTAG pins

-0.4

VCCO_0 + 0.55

V

Xilinx datasheet DS181

Storage temperature

-40

+85100

°C

-


Recommended Operating Conditions

Scroll Title
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titleRecommended Operating Conditions

This TRM is generic for all variants.

Variants of modules are described here: Article Number Information

Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C

Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C

Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C

The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

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ParameterMinMaxUnitsReference Document
VIN supply voltage3.1353.45V-
HR I/O banks supply voltage (VCCO)1.143.465VXilinx datasheet DS181
HR I/O banks input voltage-0.20VCCO + 0.2020VVXilinx datasheet DS181
Voltage on module JTAG pins3.1353.4650VCCO_0 + 5%VXilinx datasheet DS181


Physical Dimensions

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Scroll Title
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titleDocument change history

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Sept 2018

Date

Revision

Authors

Description

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dateFormatyyyy-MM-dd

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  • Updated storage temperatur.
2021-04-07v59Thomas Steffens
  • changed operating conditions
2019-03-04v55John Hartfiel
  • Restore and modify v.50
  • Correction max IO count on key features
  • Change history table
  • typo correction
2019-01-07v.50John Hartfiel
  • Updated to TRM version 2.2
  • Style modifications

2018-09-19

v.48Martin Rohrmüller
  • Updated to TRM version 2.1
  • Updated B2B Connectors
  • Style modifications
2018-09-17

v.38

Martin Rohrmüller
  • Added power rail section
  • Added Rev 02 Flash PCN
  • Corrected table headings
2018-09-17v.36Martin Rohrmüller

  • Update to TRM version 2.0 with DrawIO Figures

  • Added Figure Power Distribution
2018-04-04

v.35

Martin RohrmüllerCorrected clock net designator in table.
2017-05-28

v.27

Jan Kumann
  • Board-to-Board I/O section added.
  • New physical dimensions images.
  • Documents sections rearranged.
2017-03-20

v.26

John Hartfiel
  • Notes on Clocking section.
2017-01-27v.25Jan Kumann
  • New block diagram.
2016-12-01

v.17

Jan Kumann
  • Changes in the document structure, few corrections.
2016-11-18
v.14

Thorsten Trenz, Emmanuel Vassilakis

  • Hardware revision 02 specific changes.

2016-06-01

v.9

Antti Lukats

  • Initial version.
--all

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