Page History

Key Features

• Xilinx Artix-7 (A15T, A35T, A50T)

• Rugged for shock and high vibration
• 16 MByte QSPI Flash memory
• Differential MEMS Oscillator for GT Clocking
• MEMS Oscillator for PL Clocks (option)
• Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
  • 144 FPGA I/Os (
  68 LVDS pairs possible, Analog 1 x ADC) available on board-to-board connectors
  • max 68 differential)
  • XADC Analog Input
  • 4 GTP (high-performance transceiver) lanesGTP (high-performance transceiver) clock input
  • GT Reference Clock input
  • Optimized I/O and power pins for good signal integrity
• On-board high-efficiency DC-DC converters
  • 3 A x 1.35 V power rail
  • 3 A x 1 V power rail
  • 1.5 A x 1 V power rail
  • 1.5 A x 1.2 V power rail
  • 600 mA x 1.8 V power rail
  System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• LED
• (AES)
• One user LEDEvenly-spread supply pins for good signal integrity
  
  

Assembly options for cost or performance optimization available upon request. Possible options:

• FPGA Type (A15T, A35T, A50T), temperature grade
• GT Clock Frequency (or none if not assembled)
• PL Clock Frequency and precision or none if not assembled)
• Config and B14 Bank Voltage: 1.8V or 3.3V
• SPI Flash type (or none if not assembled)
• LED Color (or none if not assembled)
• PUDC Pin strapping (pull high or pull down)
• GT Power Enable pin strapping (default power enabled or disabled)

Current Assembly Variants

Signals, Interfaces and Pins