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On https://wiki.trenz-electronic.de/display/PD/TE0715 the onlineOnline version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/TE0715 |
The Trenz Electronic TE0715 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (
...
XC7Z015 or
...
XC7Z030)
...
with 1GB of DDR3 SDRAM, 32MB of SPI flash memory, gigabit Ethernet PHY transceiver
...
, a USB PHY transceiver and powerful
...
switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips.
...
Block diagram
...
Main components
Main Components:
...
Zynq-7000 All Programmable SoC
...
System Controller CPLD
...
Programmable clock generator
1. Zynq-7000 all programmable SoC.
2. System controller CPLD.
3. Programmable clock generator.
4. 10/100/1000 Mbps
...
Ethernet PHY.
5. DDR3-SDRAM.
6. Hi-Speed USB 2.0 ULPI
...
transceiver.
...
B2B-Connector
JM1
JM2
JM3
7a. B2B connector JM1.
7b. B2B connector JM2.
7c. B2B connector JM3.
8. 256 Mbit (32 Mbyte) 3.0V SPI flash memory.
9. Low power RTC with battery backed SRAM.
10. PowerSoC DC-DC converter.
Key features
...
Industrial-grade Xilinx Zynq-7000 (
...
XC7Z015, XC7Z030) SoM
- Rugged for shock and high vibration
- 2 × ARM Cortex-A9
- 10/100/1000 tri-speed gigabit Ethernet transceiver PHY
- MAC
...
- address EEPROM
- 32-Bit wide
...
- 1GB DDR3 SDRAM
- 32 MByte QSPI
...
- flash memory
- Programmable
...
- clock generator
- Transceiver
...
- clock (default 125 MHz)
- Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
- 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on
...
- B2B connectors
- 4 GTP/GTX (high-performance transceiver) lanes
- GTP/GTX (high-performance transceiver) clock input
- USB 2.0 high-speed ULPI transceiver
- On-board high-efficiency DC-DC converters
- 4.0 A x 1.0 V power rail
- 1.5 A x 1.5 V power rail
- 1.5 A x 1.8 V power rail
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- User LED
- Evenly-spread supply pins for good signal integrity
...
Additional assembly options are available for cost or performance optimization
...
upon request.
Signals, Interfaces and Pins
System Controller I/O Pins
Special purpose pins used by TE0720 are also available on TE0715 they are connected to smaller System Controller CPLD and have different or no function in default configuration.
| Name | Note |
|---|---|
| EN1 | No hard wired function on PCB, when forced low pulls POR_B low to emulate power on reset |
| PGOOD | Driven low by System Controller if power supply power fail detected |
| NOSEQ | No function |
| RESIN | Active low reset, gated to POR_B |
| JTAGEN | Low for normal operation |
Boot Modes
By default the TE-0715 supports QSPI and SD boot modes.
Two boot modes are controlled by the MODE signal on the board to board (B2B) connector:
MODE signal | Boot Mode |
|---|---|
high or open | SD Card |
low or ground | QSPI |
JTAG
JTAG access to the Xilinx Zynq-7000 device is provided through connector JM2.
Signal | B2B Pin |
|---|---|
| TCK | JM2: 99 |
| TDI | JM2: 95 |
| TDO | JM2: 97 |
| TMS | JM2: 93 |
| Note |
|---|
| JTAGEN pin in JM1 should be kept low or grounded for normal operation. |
Clocking
Clock | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
PS CLK | 33.3333 Mhz | U11 | PS_CLK | PS Subsystem main clock |
ETH PHY reference | 25 MHz | U9 | - | |
USB PHY reference | 52 MHz | U15 | - | |
PLL reference | 25 MHz | U18 | - | |
GT REFCLK0 | - | B2B | U9/V9 | Externally supplied from base |
GT REFCLK1 | 125 Mhz | U10 Si5338 | U5/V5 | Default clock is 125 MHz |
Processing System (PS) Peripherals
| IC | Designator | PS7 | MIO | Notes | |
|---|---|---|---|---|---|
| SPI Flash | S25FL256SAGBHI20 | U14 | QSPI0 | MIO1..MIO6 | |
| EEPROM I2C | 24AA025E48 | U19 | I2C1 | MIO48, MIO49 | EEPROM for MAC Address |
| RTC | ISL2020 | U16 | I2C1 | MIO48, MIO49 | Temperature compensated real time clock |
| RTC Interrupt | ISL2020 | U16 | GPIO | MIO47 | Real Time Clock Interrupt |
| Clock PLL | Si5338 | U10 | I2C1 | MIO48, MIO49 | Low jitter phase locked loop |
| LED | D4 | GPIO | MIO7 | ||
| USB | USB3320 | U6 | USB0 | MIO28..MIO39 | |
| USB Reset | GPIO | MIO51 | |||
| Ethernet | 88E1512 | U7 | ETH0 | MIO16..MIO27 | |
| Ethernet Reset | GPIO | MIO50 |
Default MIO mapping:
Initial Delivery State
Storage device name | Content | Notes |
|---|---|---|
24AA025E48 EEPROM | User content not programmed | Valid MAC Address from manufacturer. |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor. |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | Demo design | - |
EFUSE USER | Not programmed | - |
EFUSE Security | Not programmed | - |
Interfaces and Pins
Board to Board (B2B) I/O's
I/O signals connected to the SoC's I/O bank and B2B connector:
| Bank | Type | B2B Connector | I/O Signal Count | Voltage | Notes |
|---|---|---|---|---|---|
13 | HR | JM1 | 48 | User | - |
34 | HR/HP | JM2 | 18 | User | 1.8V max with XC7Z030! |
35 | HR/HP | JM2 | 50 | User | 1.8V max with XC7Z030! |
34 | HR/HP | JM3 | 16 | User | 1.8V max with XC7Z030! |
500 | MIO | JM1 | 8 | 3.3V | - |
501 | MIO | JM1 | 6 | 1.8V | - |
112 | GT | JM3 | 4 Lanes | N/A | - |
112 | GT CLK | JM3 | One Differential Input | N/A | NB! AC coupling capacitors on baseboard required. |
For detailed information about the pin out, please refer to the Master Pinout Table.
Default MIO Mapping
| MIO | Function | B2B Pin | Notes | MIO | Function | B2B Pin | Notes | |
|---|---|---|---|---|---|---|---|---|
| 0 | GPIO | JM1-87 | B2B | 16..27 | ETH0 | - | RGMII | |
| 1 | QSPI0 | - | SPI Flash-CS | 28..39 | USB0 | - | ULPI | |
| 2 | QSPI0 | - | SPI Flash-DQ0 | 40 | SDIO0 | JM1-27 | B2B | |
| 3 | QSPI0 | - | SPI Flash-DQ1 | 41 | SDIO0 | JM1-25 | B2B | |
| 4 | QSPI0 | - | SPI Flash-DQ2 | 42 | SDIO0 | JM1-23 | B2B | |
| 5 | QSPI0 | - | SPI Flash-DQ3 | 43 | SDIO0 | JM1-21 | B2B | |
| 6 | QSPI0 | - | SPI Flash-SCK | 44 | SDIO0 | JM1-19 | B2B | |
| 7 | GPIO | - | Green LED D4 | 45 | SDIO0 | JM1-17 | B2B | |
| 8 | QSPI0 | - | SPI Flash-SCKFB | 46 | GPIO | - | Ethernet PHY LED2 INTn Signal. | |
| 9 | JM1-91 | B2B | 47 | GPIO | - | RTC Interrupt | ||
| 10 | JM1-95 | B2B | 48 | I2C1 | - | SCL on-board I2C | ||
| 11 | JM1-93 | B2B | 49 | I2C1 | - | SDA on-board I2C | ||
| 12 | JM1-99 | B2B | 50 | GPIO | - | ETH0 Reset | ||
| 13 | JM1-97 | B2B | 51 | GPIO | - | USB Reset | ||
| 14 | UART0 | JM1-92 | B2B | 52 | ETH0 | - | MDC | |
| MIO | Configured as | B2B | Notes | |||||
| 0 | GPIO | JM1-87 | B2B | |||||
| 1 | QSPI0 | - | SPI Flash-CS | |||||
| 2 | QSPI0 | - | SPI Flash-DQ0 | |||||
| 3 | QSPI0 | - | SPI Flash-DQ1 | |||||
| 4 | QSPI0 | - | SPI Flash-DQ2 | |||||
| 5 | QSPI0 | - | SPI Flash-DQ3 | |||||
| 6 | QSPI0 | - | SPI Flash-SCK | |||||
| 7 | GPIO | - | Green LED D4 | |||||
| 8 | QSPI0 | - | SPI Flash-SCKFB | |||||
| 9 | JM1-91 | B2B | ||||||
| 10 | JM1-95 | B2B | ||||||
| 11 | JM1-93 | B2B | ||||||
| 12 | JM1-99 | B2B | ||||||
| 13 | JM1-97 | B2B | ||||||
| 14 | UART0 | JM1-92 | B2B | |||||
| 15 | UART0 | JM1-85 | B2B | 16..27 | ETH0 | RGMII | ||
| 28..39 | USB0 | ULPI | ||||||
| 40 | SDIO0 | JM1-27 | B2B | |||||
| 41 | SDIO0 | JM1-25 | B2B | |||||
| 42 | SDIO0 | JM1-23 | B2B | |||||
| 43 | SDIO0 | JM1-21 | B2B | |||||
| 44 | SDIO0 | JM1-19 | B2B | |||||
| 45 | SDIO0 | JM1-17 | B2B | |||||
| 46 | GPIO | - | Ethernet PHY LED2/INTn Signal | |||||
| 47 | GPIO | - | RTC Interrupt | |||||
| 48 | I2C1 | - | SCL on-board I2C | |||||
| 49 | I2C1 | - | SDA on-board I2C | |||||
| 50 | GPIO | - | ETH0 Reset | |||||
| 51 | GPIO | - | USB Reset | |||||
| 52 | ETH0 | - | MDC | |||||
53 | ETH0 | - | MDIO |
I2C Interface
The on-board I2C components are connected to MIO48 and MIO49 and configured as I2C1 by default.
I2C addresses for on-board components:
| 53 | ETH0 | - | MDIO |
|---|
Gigabit Ethernet
On board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an onboard 25MHz oscillator (U9), the 125MHz output clock is connected to IN5 of the PLL chip (U10).
Ethernet PHY connection
| PHY Pin | ZYNQ PS | ZYNQ PL | Notes |
|---|---|---|---|
| MDC/MDIO | MIO52, MIO53 | - | - |
| LED0 | - | J3 | Can be routed via PL to any free PL I/O pin in B2B connector. |
| LED1 | - | K8 | Can be routed via PL to any free PL I/O pin in B2B connector. This LED is connected to PL via level-shifter implemented in system controller CPLD. |
| LED2/Interrupt | MIO46 | - | - |
| CONFIG | - | - | By default the PHY address is strapped to 0x00, alternate configuration is possible. |
| RESETn | MIO50 | - | - |
| RGMII | MIO16..MIO27 | - | - |
| SGMII | - | - | on B2B. |
| MDI | - | - | on B2B. |
USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an onboard 52MHz oscillator (U15).
USB PHY connection
| PHY Pin | ZYNQ Pin | B2B Name | Notes |
|---|---|---|---|
| ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY. |
| REFCLK | - | - | 52MHz from on board oscillator (U15). |
| REFSEL[0..2] | - | - | Reference clock frequency select, all set to GND selects 52MHz. |
| RESETB | MIO51 | - | Active low reset. |
| CLKOUT | MIO36 | - | Connected to 1.8V, selects reference clock operation mode. |
| DP, DM | - | OTG_D_P, OTG_D_N | USB data lines. |
| CPEN | - | VBUS_V_EN | External USB power switch active high enable signal. |
| VBUS | - | USB_VBUS | Connect to USB VBUS via a series of resistors, see reference schematics. |
| ID | - | OTG_ID | For an A-Device connect to ground, for a B-Device left floating. |
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
I2C Interface
On-board I2C devices are connected to MIO48 and MIO49 which are configured as I2C1 by default. I2C addresses for on-board devices are listed in the table below:
| I2C Device | I2C Adress | Device | I2C-AddressNotes | |
|---|---|---|---|---|
| EEPROM | 0x50 | |||
| RTC | 0x6F | |||
| Battery backed RAM | 0x57 | integrated in Integrated into RTC. | ||
PLL | 0x70 |
B2B I/O
Number of I/O's connected to the SoC's I/O bank and B2B connector:
Bank | Type | JMx | IO Count | IO Voltage | Notes |
|---|---|---|---|---|---|
13 | HR | 1 | 48 | User | |
34 | HR/HP | 2 | 18 | User | 1.8V max with Z7030 |
35 | HR/HP | 2 | 50 | User | 1.8V max with Z7030 |
34 | HR/HP | 3 | 16 | User | 1.8V max with Z7030 |
500 | MIO | 1 | 8 | 3.3V | |
501 | MIO | 1 | 6 | 1.8V | |
112 | GT | 3 | 4 Lanes | n/a | |
112 | GT CLK | 3 | one differential input | n/a | AC coupling capacitors on base required |
For detailed information about the pin out, please refer to the Master Pinout Table.
Peripherals
LED's
...
JTAG Interface
JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.
JTAG Signal | B2B Connector Pin |
|---|---|
| TCK | JM2-99 |
| TDI | JM2-95 |
| TDO | JM2-97 |
| TMS | JM2-93 |
| Note |
|---|
| JTAGEN pin in B2B connector JM1 should be kept low or grounded for normal operation. |
System Controller I/O Pins
Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:
| Pin Name | Mode | Function | Default Configuration |
|---|---|---|---|
| EN1 | Input | Power Enable | No hard wired function on PCB, when forced low pulls POR_B low to emulate power on reset. |
| PGOOD | Output | Power Good | Active high when all on-module power supplies are working properly. |
| NOSEQ | - | - | No function. |
| RESIN | Input | Reset | Active low reset, gated to POR_B. |
| JTAGEN | Input | JTAG Select | Low for normal operation. |
Boot Mode Pin
By default the TE-0715 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.
MODE Signal State | Boot Mode |
|---|---|
high or open | SD Card |
low or ground | QSPI |
LED's
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
D2 | greenGreen | DONE | Inverted Reflects inverted DONE signal, ON when FPGA is not configured |
D3 | red | SC | Global status LED |
D4 | green | MIO7 | OFF when PS7 not booted and not controlling MIO7 by software, else user controlled |
...
OFF |
...
as soon as PL is configured. This LED will not operate if the SC can not power on the 3.3V output |
...
Ethernet
The TE0715 is populated with a Marvell Alaska 88E1512 Gigabit Ethernet PHY. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. The I/O Voltage is fixed at 1.8V for HSTL signaling.
SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3.
The reference clock input of the PHY is supplied from an on board 25MHz oscillator (U9), the 125MHz output clock is connected to IN5 of the PLL chip (U10).
PHY connection:
PHY PIN | ZYNQ PS | ZYNQ PL | Notes |
|---|---|---|---|
| MDC/MDIO | MIO52, MIO53 | - | - |
| LED0 | - | J3 | can be routed via PL to any free PL I/O pin in B2B connector |
| LED1 | - | K8 | can be routed via PL to any free PL I/O pin in B2B connector |
| LED2/Interrupt | MIO46 | - | - |
| CONFIG | - | - | By default the PHY Address is strapped to 0x00 alternate configuration is possible |
| RESETn | MIO50 | - | - |
| RGMII | MIO16..MIO27 | - | - |
| SGMII | - | - | on B2B |
| MDI | - | - | on B2B |
Note: LED1 is connected to PL via level-shifter implemented in system controller CPLD.
USB
The USB PHY USB3320 from Microchip is used on the TE0715. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V.
The reference clock input of the PHY is supplied from an on board 52MHz oscillator (U15).
PHY connection:
PHY Pin | Zynq Pin | B2B Name | Notes |
|---|---|---|---|
| ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY |
| REFCLK | - | - | 52MHz from on board oscillator (U15) |
| REFSEL[0..2] | - | - | 000 GND, select 52MHz reference Clock |
| RESETB | MIO51 | - | Active low reset |
| CLKOUT | MIO36 | - | Connected to 1.8V selects reference clock operation mode |
| DP,DM | - | OTG_D_P, OTG_D_N | USB Data lines |
| CPEN | - | VBUS_V_EN | External USB power switch active high enable signal |
| VBUS | - | USB_VBUS | Connect to USB VBUS via a series resistor. Check reference schematic |
| ID | - | OTG_ID | For an A-Device connect to ground, for a B-Device left floating |
The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
RTC
An Intersil temperature compensated real time clock IC ISL12020M is used for timekeeping (U16). Battery voltage must be supplied to the module from the main board.
Battery backed registers are accessed at I2C slave address 0x6F.
General purpose RAM is accessed at I2C slave address 0x57.
This RTC IC is supported in Linux so it can be used as hwclock device.
PLL
A Silicon Labs I2C-programmable clock generator Si5338A (U10) is populated on the module. The Si5338 can be programmed using the I2C-bus, to change the frequency on its outputs. It is accessible on the I2C slave address 0x70.
PLL connection:
Input/Output | Default Frequency | Notes |
|---|---|---|
IN1/IN2 | Externally supplied | need decoupling on base board |
IN3 | 25MHz | Fixed input clock |
IN4 | - | not available and not used |
IN5/IN6 | 125MHz | Ethernet PHY output clock |
CLK0 | - | not used, disabled |
CLK1 | - | not used, disabled |
CLK2 A/B | 125MHz | MGT reference clock 1 |
CLK3A | 125MHz | Bank 34 clock input |
CLK3B | - | not used, disabled |
MAC-Address EEPROM
A Microchip 24AA025E48 EEPROM (U19) is used on the TE0715. It contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM). The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.
Power
| Warning |
|---|
TE0715-xx-30 has several HP banks on B2B Connectors, those banks have maximal Voltage tolerance of 1.8V please check special instructions for the Baseboard use with TE0715-xx-30 |
For startup, a power supply with minimum current capability of 3A is recommended.
| Note |
|---|
VIN and 3.3VIN can be connected to the same source (3.3 V). |
Power Supplies
...
Vin
...
3.3 V to 5.5 V
...
Typical 200 mA, depending on customer design and connections
rail that also powers the 3.3V circuitry on the module. | |||
D3 | Red | SC | System main status LED. |
D4 | Green | MIO7 | User controlled, default OFF (when PS7 has not been booted). |
Onboard Peripherals
Processing System (PS) Peripherals
| Name | IC | ID | PS7 | MIO | Notes |
|---|---|---|---|---|---|
| SPI Flash | S25FL256SAGBHI20 | U14 | QSPI0 | MIO1..MIO6 | |
| EEPROM I2C | 24AA025E48 | U19 | I2C1 | MIO48, MIO49 | EEPROM for MAC Address. |
| RTC | ISL2020 | U16 | I2C1 | MIO48, MIO49 | Temperature compensated RTC. |
| RTC Interrupt | ISL2020 | U16 | GPIO | MIO47 | Real Time Clock Interrupt. |
| Clock PLL | Si5338 | U10 | I2C1 | MIO48, MIO49 | Low jitter phase locked loop. |
| LED | - | D4 | GPIO | MIO7 | |
| USB | USB3320 | U6 | USB0 | MIO28..MIO39 | |
| USB Reset | - | - | GPIO | MIO51 | |
| Ethernet | 88E1512 | U7 | ETH0 | MIO16..MIO27 | |
| Ethernet Reset | - | - | GPIO | MIO50 |
Clocking
| Clock | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
PS CLK | 33.3333 Mhz | U11 | PS_CLK | PS subsystem main clock. |
ETH PHY reference | 25 MHz | U9 | - | - |
USB PHY reference | 52 MHz | U15 | - | - |
PLL reference | 25 MHz | U18 | - | - |
GT REFCLK0 | - | B2B | U9/V9 | Externally supplied from baseboard. |
GT REFCLK1 | 125 Mhz | U10 Si5338 | U5/V5 | Default clock is 125 MHz. |
RTC - Real Time Clock
An temperature compensated Intersil ISL12020M is used for Real Time Clock (U16). Battery voltage must be supplied to the module from the main board. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.
PLL - Phase-Locked Loop
There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70.
PLL connection
| I/O | Default Frequency | Notes |
|---|---|---|
IN1/IN2 | Externally supplied | Needs decoupling on base board. |
IN3 | 25MHz | Fixed input clock. |
IN4 | - | - |
IN5/IN6 | 125MHz | Ethernet PHY output clock. |
CLK0 | - | Not used, disabled. |
CLK1 | - | Not used, disabled. |
CLK2 A/B | 125MHz | MGT reference clock 1. |
CLK3A | 125MHz | Bank 34 clock input. |
CLK3B | - | Not used, disabled. |
MAC-Address EEPROM
A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.
Power and Power-On Sequence
| Warning |
|---|
TE0715-xx-30 has several HP banks on B2B connectors. Those banks have maximum voltage tolerance of 1.8V. Please check special instructions for the baseboard to be used with TE0715-xx-30. |
Power Supply
Power supply with minimum current capability of 3A for system startup is recommended.
Power Consumption
| Power Input Pin | Max Current |
|---|---|
| VIN | TBD* |
| 3.3VIN | TBD* |
* TBD - To Be Determined soon with reference design setup.
Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise, this is due to the DC/DC converter efficiency (it decreases when VIN/VOUT ratio rises). Typical power consumption is between 2-3W.
Power-On Sequence
For highest efficiency of on board DC/DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.
It is important that all baseboard I/O's are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 module.
...
Vin 3.3V
...
3.3 V
...
Bank Voltages
Bank | Voltage | TE0715-xx-15 | TE0715-xx-30 |
|---|---|---|---|
500 MIO0 | 3.3V | - | - |
501 MIO1 | 1.8V | - | - |
502 DDR | 1.5V | - | - |
0 Config | 3.3V | - | - |
13 HR | User | Max 3.3V | Max 3.3V |
34 HR/HP | User | Max 3.3V | Max 1.8V |
35 HR/HP | User | Max 3.3V | Max 1.8V |
Initial Delivery state
Storage device name | Content | Notes |
|---|---|---|
24AA025E48 EEPROM | User content not programmed | Valid MAC Address from manufacturer |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash Quad Enable bit | Programmed | |
SPI Flash main array | demo design | |
EFUSE USER | Not programmed | |
EFUSE Security | Not programmed |
Hardware Revision History
| Revision | Changes |
|---|---|
01 | Prototypes |
| 02 | Prototypes |
| 03 | First production release |
Technical Specification
Absolute Maximum Ratings
Parameter | Min | Max | Units | Notes |
|---|---|---|---|---|
Vin supply voltage | -0.3 | 6.0 | V | |
Vin33 supply voltage | -0.4 | 3.6 | V | |
| VBat supply voltage | -1 | 6.0 | V | |
| PL IO Bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | V | |
PL IO Bank supply voltage for HP I/O banks (VCCO) | -0.5 | 2.0 | V | TE0715-xx-15 does not have HP banks |
| I/O input voltage for HR I/O banks | -0.4 | VCCO_X+0.55 | V | |
| I/O input voltage for HP I/O banks | -0.55 | VCCO_X+0.55 | V | TE0715-xx-15 does not have HP banks |
| GT Receiver (RXP/RXN) and Transmitter (TXP/TXN) | -0.5 | 1.26 | V | |
Voltage on Module JTAG pins | -0.4 | VCCO_0+0.55 | V | VCCO_0 is 3.3V nominal |
Storage Temperature | -40 | +85 | C | |
| Storage Temperature without the ISL12020MIRZ | -55 | +100 | C |
| Note |
|---|
| Assembly variants for higher storage temperature range on request |
| Note |
|---|
| Please check Xilinx Datasheet for complete list of Absolute maximum and recommended operating ratings for the Zynq device (DS181 Artix or DS182 Kintex). |
Recommended Operating Conditions
| Parameter | Min | Max | Units | Notes | Reference document |
| Vin supply voltage | 2.5 | 5.5 | V | ||
| Vin33 supply voltage | 3.135 | 3.465 | V | ||
| VBat supply voltage | 2.7 | 5.5 | V | ||
| PL IO Bank supply voltage for HR I/O banks (VCCO) | 1.14 | 3.465 | V | Xilinx document DS191 | |
| PL IO Bank supply voltage for HP I/O banks (VCCO) | 1.14 | 1.89 | V | TE0715-xx-15 does not have HP banks. | Xilinx document DS191 |
| I/O input voltage for HR I/O banks | (*) | (*) | V | (*) Check datasheet | Xilinx document DS191 and DS187 |
| I/O input voltage for HP I/O banks | (*) | (*) | V | TE0715-xx-15 does not have HP banks. (*) Check datasheet | Xilinx document DS191 |
| Voltage on Module JTAG pins | 3.135 | 3.465 | V | VCCO_0 is 3.3 V nominal |
Physical Dimensions
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.
All dimensions are shown in mm.
Temperature Ranges
Commercial grade modules
All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Industrial grade modules
All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Weight
26 g | Plain module |
8.8 g | Set of bolts and nuts |
Document Change History
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date
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revision
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authors
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description
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Emmanuel Vassilakis...
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Notes |
|---|---|---|---|---|
VIN supply voltage | -0.3 | 6.0 | V | - |
3.3VIN supply voltage | -0.4 | 3.6 | V | - |
| VBat supply voltage | -1 | 6.0 | V | - |
| PL IO bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | V | - |
PL IO bank supply voltage for HP I/O banks (VCCO) | -0.5 | 2.0 | V | TE0715-xx-15 does not have HP banks. |
| I/O input voltage for HR I/O banks | -0.4 | VCCO_X+0.55 | V | - |
| I/O input voltage for HP I/O banks | -0.55 | VCCO_X+0.55 | V | TE0715-xx-15 does not have HP banks. |
| GT receiver (RXP/RXN) and transmitter (TXP/TXN) | -0.5 | 1.26 | V | - |
Voltage on module JTAG pins | -0.4 | VCCO_0+0.55 | V | VCCO_0 is 3.3V nominal. |
Storage temperature | -40 | +85 | Co | - |
| Storage temperature without the ISL12020MIRZ | -55 | +100 | Co | - |
| Note |
|---|
| Assembly variants for higher storage temperature range are available on request. |
| Note |
|---|
| Please check Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for complete list of absolute maximum and recommended operating ratings. |
Recommended Operating Conditions
| Parameter | Min | Max | Units | Notes | Reference Document |
|---|---|---|---|---|---|
| VIN supply voltage | 2.5 | 5.5 | V | ||
| 3.3VIN supply voltage | 3.135 | 3.465 | V | ||
| VBAT_IN supply voltage | 2.7 | 5.5 | V | ||
PL I/O bank supply voltage for HR I/O banks (VCCO) | 1.14 | 3.465 | V | Xilinx datasheet DS191 | |
PL I/O bank supply voltage for HP I/O banks (VCCO) | 1.14 | 1.89 | V | TE0715-xx-15 does not have HP banks | Xilinx datasheet DS191 |
| I/O input voltage for HR I/O banks | (*) | (*) | V | (*) Check datasheet | Xilinx datasheet DS191 or DS187 |
| I/O input voltage for HP I/O banks | (*) | (*) | V | TE0715-xx-15 does not have HP banks (*) Check datasheet | Xilinx datasheet DS191 |
| Voltage on Module JTAG pins | 3.135 | 3.465 | V | VCCO_0 is 3.3 V nominal |
Physical Dimensions
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 8mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers
All dimensions are given in mm.
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Weight
26 g - Plain module
8.8 g - Set of bolts and nuts
Document Change History
Date | Rrevision | Contributors | Description |
|---|---|---|---|
| 2016-06-28 | New overall document layout with shorter table of contents. Revision 01 PCB pictures replaced with the revision 03 ones. Fixed link to Master Pinout Table. New default MIO mapping table design. Revised Power-on section. Added links to related Xilinx online documents. Physical dimensions pictures revised. Revision number picture with explanation added. | ||
| 2016-04-27 | V33 | Philipp Bernhardt, Antti Lukats, Thorsten Trenz, Emmanuel Vassilakis | Added the table "Recommended Operating Conditions" Storage Temperature edited. |
| 2016-03-31 | V10 | Philipp Bernhardt, Antti Lukats, Thorsten Trenz | Initial version. |
Hardware Revision History
| Date | Revision | Notes | PCN |
|---|---|---|---|
| - | 01 | Prototypes | |
| - | 02 | Prototypes | |
| - | 03 | First production release | |
| 2016-06-21 | 04 | Second production release | Click to see PCN |
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
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2016-03-31
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Disclaimer
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Disclaimer
| Include Page | ||||
|---|---|---|---|---|
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