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• Xilinx Virtex-7 FPGA module XC7VX330T-2FFG1157C (commercial temperature range)
• PCI Express 2.0 x8 card with maximum throughput of 4 GB/s
• FMC High Pin Count (HPC) connector
• 8 FPGA MGT lanes available on PCIe interface
• DDR3 SO-DIMM SDRAM socket
• 256-Mbit (32-MByte) Quad SPI Flash memory (for configuration and operation) accessible through:
  • FPGA
  • JTAG port (SPI indirect, bus width x4)
• External clock input via SMA coaxial connector
• 28 GTH transceivers, each with up to 13.1 Gbit/s data transmission rate
• FPGA configuration through:
  • JTAG connector
  • Quad SPI Flash memory
• Programmable quad clock generator
• TI LMK04828B ultra low-noise JESD204B compliant clock jitter cleaner
• On-board high-efficiency DC-DC converters
• Up to 202 FPGA I/O pins available on FMC connector (up to 101 LVDS pairs possible)
• System management and power sequencing
• AES bit-stream encryption
• eFUSE bit-stream encryption

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Block Diagram

Figure 1: TEC0330-03 Block Diagramblock diagram.

Main Components

Figure 2: FPGA board TEC0330-03.

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The I/O signals are routed from the FPGA I/O banks to the FMC connector as LVDS pairs:

Table 2: Overview of the FPGA I/O bank signals routed to the FMC.

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There are also 10 high-speed MGT lanes (Xilinx GTH transceivers) from different FPGA MGT banks routed to the FMC connector.The MGT banks have also clock input pins which are exposed to the FMC connector. Following MGT lanes are available on the FMC connector:

Table 3: Overview of MGT banks lanes routed to the FMC connector.

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The FMC connector has also two reference clock input pairs (LVDS) routed to the FPGA MGT bank 117, see also section MGT lanes.

There are also JTAG, I²C interface and power good control signals routed between FMC connector and System Controller CPLD provides JTAG and I²C interfaces to the System Controller CPLD:

Table 4:  FMC connector pin-outs of available interfaces to the System Controller CPLD.

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FPGA bank 17 and 18 clock inputs from FMC connector:

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Several VCCIO voltages are available on the FMC connector for FPGA I/O banks:

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The TEC0330 FPGA board is also a PCI Express card designed to fit in computing into systems with PCI Express x8 slots (PCIe 2.0 or higher) and is PCIe Gen. 2 capable. 8 MGT lanes are See next section for the overview of FPGA MGT lanes routed to the PCIe interface composed of .

MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one receive and one transmit (RX/TX LVDS pairs for each lane:

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MGT lanes

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1 reference clock from  programmable quad clock generator
U13 to bank's pins AB6/AB5

1 reference clock from PCIe interface J1 to bank's pins AD6/AD5

) differential pairs, four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, FMC connector pin connection and FPGA pin connection information.

FPGA to FMC Connector MGT lanes

Table 7: MGT lanes available on PCIe interface.

MGT Lanes

 MGT (Multi Gigabit Transceiver) lane consists of one receive and one transmit (RX/TX) differential pairs, four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, FMC connector pin connection and FPGA pin connection information:

FPGA to FMC MGT lanes

Table 8: FPGA to FMC connector MGT lanes overview (continue on next page).

FPGA to FMC Connector MGT lanes (continued)

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Table 8: FPGA to FMC connector MGT lanes overview (continue on next page).

FPGA to FMC PCIe Connector MGT lanes (continued)

Table 8: FPGA to FMC connector MGT lanes overview.

JTAG Interfaces

TEC0330 board JTAG interfaces accessing the FPGA or the System Controller CPLD:

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CPLD JTAG

VCCIO: 3V3PCI

Connector: J8

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J8-4

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FPGA JTAG

VCCIO: 1V8

Connector: J9

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FMC JTAG

VCCIO: 3.3VPCI

Connector: J2

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Table 9: JTAG Interface on TEC0330 board.

SO-DIMM Socket for DDR3 SDRAM

The TEC0330 board supports additional DDR3 SO-DIMM (204-pin) via 204-pin SO-DIMM socked U2. The DDR3 memory interface is routed to the FPGA banks 34, 35 and 36.

The reference clock signal for the DDR3 interface is generated by the quad programmable reference clock U13 and is applied to bank 35.

There is also a I²C interface between the System Controller CPLD and the DDR3 SDRAM memory:

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Table 10: I²C-interface between SC CPLD and DDR3 SDRAM memory.

System Controller CPLD

The System Controller CPLD is the central system management unit that provides numerous interfaces between the on-board peripherals and to the FPGA module. The signals routed to the CPLD will be linked by the logic implemented in the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. So some interfaces between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence, the proper programing of the FPGA module and to display its programming state.

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Table 11: VCCIO voltages of CPLD banks.

Following table describes the interfaces and functionalities of the System Controller CPLD, which are not described elsewhere in this TRM:

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FPGA_IIC_SDA, pin 24

FPGA_IIC_SCL, pin 25

FPGA_IIC_OE, pin 19

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FPGA bank 16, pin V29

FPGA bank 16, pin W29

FPGA bank 16, pin W26

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VCCIO: 1V8, all with pull-up to 1V8.

Following devices and connectors are linked to the FPGA_IIC I²C interface:

• DC-DC converter U3 and U4 (LT LTM4676)
• Programmable quad clock generator U13
• FMC connector J2
• PCIe connector J1

Note: FPGA_IIC_OE must kept high for I²C operation.

For I²C slave device addresses refer to the component datasheets.

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User I/Os

External LVDS pairs

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10 I/Os

5 x differential signaling pairs

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EX0_P ... EX4_P

EX0_N ... EX4_N

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Can also be used for single-ended signaling.

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User I/Os

Internal LVDS pairs

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13 I/Os

6 x differential signaling pairs

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FEX0_P ... FEX5_P

FEX0_N ... FEX5_N

FEX_DIR (single-ended I/O)

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VCCIO: 1V8

Can also be used for single-ended signaling.

FPGA bank 18 has also reference clock input from FMC connector (CLK2, CLK3) and clock synthesizer U9 (FCLK).

Internal signal assignment:

FEX_DIR <= FMC_PRSNT_M2C_L

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DONE, pin 7

PROGRAM_B, pin 8

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FPGA bank 0, pin V8

FPGA bank 0, pin U8

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PLL_SCL, pin 14

PLL_SDA, pin 15

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U13, pin 12

U13, pin 19

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VCCIO: 1V8

Only PLL_SDA has 1V8 pull-up.

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F1SENSE, pin 99

F1PWM, pin 98

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J4-3 (active low)

J4-4

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Internal signal assignment:

FEX_5_P <= F1SENSE

FEX_5_N => F1PWM

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Fast blinking, when FPGA is not programmed.

Internal signal assignment:

LED1 <= Button S2 or FEX0_P

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PCIe control line RESET_B

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Internal signal assignment:

FEX_4_N <= PCIE_RSTB

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Control Interface to clock synthesizer U9 (TI LMK04828B)

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SPI (3 I/Os),

4 I/Os

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CLK_SYNTH_SDIO, pin 75

CLK_SYNTH_SCK, pin 74

CLK_SYNTH_RESET, pin 54

CLK_SYNTH_CS, pin 53

CLK_SYNTH_SYNC, pin 52

LMK_STAT0, pin 62

LMK_STAT1, pin 63

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U9, pin 20

U9, pin 19

U9, pin 5

U9, pin 18

U9, pin 6

U9, pin 31

U9, pin 48

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Pull up to 3V3PCI.

Internal signal assignment:

LMK_SCK <= FEX_1_P

LMK_SDIO <= FEX_1_N

LMK_CS <= FEX_3_P

LMK_SYNC <= EX_3_N

LMK_RESET <= FEX_4_P

FEX_2_P => LMK_SDIO (FEX_2_N must be 0)

LMK_STAT0 and LMK_STAT1 signals are not used.

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I²C (2 I/Os),

2 I/Os

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LTM_SCL, pin 67

LTM_SDA, pin 66

LTM1_ALERT, pin 65

LTM2_ALERT, pin 64

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U4, pin E6 and U3, pin E6

U4, pin D6 and U3, pin D6

U4, pin E5

U3, pin E5

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3V3 pull-ups.

LTM I²C interface is also accessible trough header J10.

LTM1_Alert and LTM2_ALERT signals are not used.

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EN_1V8, pin 58

PG_1V8, pin 59

EN_FMC_VADJ, pin 60

PG_FMC_VADJ, pin 61

EN_3V3, pin 51

PG_3V3, pin 57

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U20, pin 27

U20, pin 28

U7, pin 27

U7, pin 28

U15, pin 27

U15, pin 28

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Sequence of the supply voltages depend on the System Controller CPLD firmware.

EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously at start-up.

PG signals will not be evaluated.

Table 12: Overview of the System Controller CPLD functions.

Clocking

The TEC0330 FPGA board has a sophisticated clock generation and conditioning system to meet the requirements of the Xilinx Virtex-7 GTH units with data transmission rates up to 13.1 Gb/s.

Clock sources

List of on-board and external reference clock signals of the TE0330 board:

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CLK_SYNTH_CLKIN0_P,

CLK_SYNTH_CLKIN0_N (GND)

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CLK0_P, CLK0_N

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GBTCLK0_M2C_P,

GBTCLK0_M2C_N

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GBTCLK1_M2C_P,

GBTCLK1_M2C_N

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PCIE_CLK_P,

PCIE_CLK_N

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100 MHz

(PCIe spec.)

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Table 13: Clock generator sources overview.

Programmable Clock Generator

There is a Silicon Labs I²C programmable quad clock generator Si5338A (U13) on-board. It's output frequencies can be programmed by using the I²C-bus with address 0x70.

A 25 MHz (U14) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.

Once running, the frequency and other parameters can be changed by programming the device using the I²C bus connected between the FPGA (master) and clock generator (slave). Logic needs to be generated inside the FPGA module to utilize I²C-bus correctly.

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IN1/IN2

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CLKIN_5338_C_P, CLKIN_5338_C_N

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Reference clock signal from clock synthesizer U9

(100 nF decoupling capacitors and 100Ω termination resistor)

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IN3

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Reference clock oscillator input, SiTime  SiT8208AI (U14).

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IN4/IN6

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IN5

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Not connected

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CLK0 A/B

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DDR3_CLK_P, DDR3_CLK_N

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CLK1 A/B

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MGTCLK_5338_C_P,

MGTCLK_5338_C_N

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Reference clock signal to FPGA bank 115 MGT

(100 nF decoupling capacitors and 100Ω termination resistor)

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CLK2 A/B

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Input clock signal to clock synthesizer U9

(100 nF decoupling capacitors)

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MGTCLK2_5338_C_P,

MGTCLK2_5338_C_N

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Reference clock signal to FPGA bank 118 MGT

(100 nF decoupling capacitors and 100Ω termination resistor)

Table 14: I/O pin description of programmable clock generator Si5338A.

Ultra low-noise high-performance clock synthesizer

The TEC0330 board utilizes an ultra low jitter clock synthesizer TI LMK04828B (U9) for conditioning and generating clean clock signals which are necessary for the GTH units of the Xilinx Virtex-7 FPGA module.

The clock synthesizer can be controlled and programmed by its SPI interface (SPI slave) and other control lines, which are routed to the FPGA module (SPI master) and by-passed trough the System Controller CPLD. See section 'System Controller CPLD' for more detailed information.

Logic needs to be generated inside the FPGA module to utilize SPI bus correctly.

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SPI interface and control lines

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CLK_SYNTH_CLKIN0_P,

CLK_SYNTH_CLKIN0_N

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Input reference clock signal via SMA coaxial connector J3, connected to CLKin0* via serial decoupling capacitor 100nF.

CLKin0 to connected to GND via serial decoupling capacitor 100nF. 

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CLK_SYNTH_CLKIN1_P,

CLK_SYNTH_CLKIN1_N

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CLK_SYNTH_DCLKOUT0_P,

CLK_SYNTH_DCLKOUT0_N

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CLK_SYNTH_SDCLKOUT1_P,

CLK_SYNTH_SDCLKOUT1_N

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CLKIN_5338_P,

CLKIN_5338_N

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Reference clock signal to programmable quad clock generator Si5338A (U13)

(100 nF decoupling capacitors and 100Ω termination resistor)

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CLK_SYNTH_DCLKOUT4_P,

CLK_SYNTH_DCLKOUT4_N

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CLK_SYNTH_SDCLKOUT7_P,

CLK_SYNTH_SDCLKOUT7_N

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CLK_SYNTH_CLKIN2_P,

CLK_SYNTH_CLKIN2_N

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Reference clock signal to FPGA bank 18, pins J30/J31

(100 nF decoupling capacitors)

Table 9: FPGA to PCIe connector MGT lanes overview.

Following table lists reference clock sources of the MGT banks.

Table 10: MGT banks reference clock sources.

JTAG Interfaces

There are three JTAG interfaces available on the TEC0330 board:

Table 11: JTAG interfaces on TEC0330 board.

On-board Peripherals

System Controller CPLD

The System Controller CPLD is the central system management unit that provides numerous interfaces between the on-board peripherals and to the FPGA module. The signals routed to the CPLD will be linked by the logic implemented in the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. So some interfaces between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence, the proper programing of the FPGA module and to display its programming state.

Table 12: VCCIO voltages of CPLD banks.

Following table describes the interfaces and functionalities of the System Controller CPLD not described elsewhere in this TRM:

Table 13: Overview of the System Controller CPLD functions.

SO-DIMM Socket for DDR3 SDRAM

The TEC0330 board supports additional DDR3 SO-DIMM via 204-pin socket U2. The DDR3 memory interface is routed to the FPGA banks 34, 35 and 36.

The reference clock signal for the DDR3 interface is generated by the quad programmable clock generator U13 and is applied to the FPGA bank 35.

There is also a I²C interface between the System Controller CPLD and the DDR3 SDRAM memory:

Table 14: I²C-interface between SC CPLD and DDR3 SDRAM memory.

Quad SPI Flash Memory

An 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron N25Q256A, U12) is provided for FPGA configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency. The memory can be accessed indirectly by the FPGA JTAG port (J9) by implementing the functional logic for this purpose inside the FPGA.

Clock sources

The TEC0330 FPGA board has a sophisticated clock generation and conditioning system to meet the requirements of the Xilinx Virtex-7 GTH units with data transmission rates up to 13.1 Gb/s.

List of on-board and external reference clock signals of the TE0330 board:

Table 15: Clock generator sources overview.

Programmable Clock Generator

There is a Silicon Labs I²C programmable quad clock generator Si5338A (U13) on-board. It's output frequencies are programmable via FPGA I²C interface using slave device address 0x70 (corresponding I²C logic has to be implemented in FPGA design).

A 25 MHz (U14) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.

Table 16: I/O pin description of programmable clock generator Si5338A.

Ultra low-noise high-performance clock synthesizer

The TEC0330 board utilizes an ultra low jitter clock synthesizer TI LMK04828B (U9) for conditioning and generating clean clock signals which are necessary for the GTH units of the Xilinx Virtex-7 FPGA module.

The clock synthesizer can be controlled and programmed by its SPI interface (SPI slave) and other control lines, which are routed to the FPGA module (SPI master) and by-passed trough the System Controller CPLD. See section 'System Controller CPLD' for more detailed information.

Logic needs to be generated inside the FPGA module to utilize SPI bus correctly.

Table 17: Pin description of clock synthesizer TI LMK04828B

Table 15: Pin description of clock synthesizer TI LMK04828B.

32 MByte Quad SPI Flash Memory

An 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron N25Q256A, U12) is provided for FPGA configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency. The memory can be accessed indirectly by the FPGA JTAG port (J9) by implementing the functional logic for this purpose inside the FPGA.

Power and Power-On Sequence

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Table 1618: Maximum current of Typical power suppliesconsumption.

TBD  - To Be Determined.

Power-On Sequence

The on-board voltages of the TEC0330 FPGA board will be are powered up in order of a determined predefined sequence after the external voltages 12V on connector J5 and 3V3PCI on connector J1 are become available.

Core voltages and main supply voltages have to reach stable state and their "Power Good" - signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.

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Table 1719: Range of FPGAs bank voltages.

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Table 1820: Power rails and corresponding connectors of the FPGA board.

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Table 1921: Absolute maximum ratings.

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Table 2022: Recommended operation conditions.

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All dimensions are given in millimeters.

Image Modified

Figure 4: Physical dimensions of the TEC0330-03 board.

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156 g - Plain board.

Revision History

Hardware Revision History

Table 2123: Hardware revision history.

Hardware revision number is printed on the PCB board together with the model number separated by the dash.

Figure 5: TE0330 board hardware revision number.

Document Change History

Table 2224: Document change history.

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