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Refer to https://wiki.trenz-electronic.de/display/PD/TE0712+TRM for online version of this manual and the rest of available documentation. |
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Trenz Electronic TE0712 is an industrial-grade FPGA module integrating a Xilinx Artix-7 FPGA, a 10/100 Mbit Ethernet transceiver, 1 GByte of DDR3 SDRAM, 32 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.
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- Xilinx Artix-7 FPGA (15T to 200T) supported by the free Xilinx Vivado WebPACK software
- Both industrial and commercial temperature ranges available
- Rugged for high shock resistance and high vibration
- 1 GByte DDR3 32-bit SDRAM
- 10/100 Mbit Ethernet PHY
- MAC address EEPROM
- 32 MByte QSPI Flash memory (with XiP support)
- Programmable clock generator
- Transceiver clock (default 125 MHz)
- Fabric clock (default 200 MHz)
- Transceiver clock (default 125 MHz)
- Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
- 158 FPGA I/Os (78 differential pairs) available via board-to-board connectors (quantity depends on assembly variant)
- 4 GTP (high-performance transceiver) lanes
- GTP (high-performance transceiver) clock input
- On-board high-efficiency DC-DC converters
- 12A x 1.0V power rail
- 1.5A x 1.8V power rail
- 1.5A x 1.5V power rail
- System management and power sequencing
- eFUSE bit-stream encryption
- AES bit-stream encryption
- User configurable LEDs
- Evenly-spread supply pins for good signal integrity
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Main Components
Programmable oscillator @25 MHz, SiTime SiT8008, U9
Programmable quad clock generator, Silicon Labs Si5338, U2
10/100 Mbps Ethernet PHY transceiver, Texas Instruments TLK106, U5
Xilinx Artix-7 FPGA XC7A series, U1
32 MByte QSPI Flash memory, Cypress S25FL256S, U4
4 Gbit DDR3 SDRAM, Intelligent Memory IM4G16D3EABG, U15
System Controller CPLD, Lattice Semiconductor MachXO2-256HC, U3
4 Gbit DDR3 SDRAM, Intelligent Memory IM4G16D3EABG, U19
Serial EEPROM, Microchip 11AA02E48, U7
- Samtec Razor Beam™ LSHM-150 B2B connector, JM2
- Samtec Razor Beam™ LSHM-150 B2B connector, JM1
- Samtec Razor Beam™ LSHM-150 B2B connector, JM3
- 12A Enpirion EN63A0QI PowerSoC DC-DC converter, U14
- Green LED (SYSLED1), D1
- Red LED (SYSLED2), D2
Initial Delivery State
Programmable unit | Content | Notes |
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Xilinx Artix-7 FPGA | Not programmed | U1 |
System Controller CPLD | Programmed | U3 |
SPI Flash OTP area | Empty | U4 |
SPI Flash main array | Empty | U4 |
SPI Flash Quad Enable bit | Set | U4 |
Microchip 11AA02E48 | Globally unique EUI-48 (Ethernet MAC address) | U7 |
Programmable quad clock generator, Silicon Labs Si5338 | Programmed, CLK1A - 50M, CLK2 - 125M, CLK3 - 50M | U2 |
Signals, Interfaces and Pins
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FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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13 | JM1 | 10 | VCCIO13 | Supplied by the baseboard. Not available on XC7A35T assembly variant. |
13 | JM3 | 20 | VCCIO13 | Supplied by the baseboard. Not available on XC7A35T assembly variant. |
14 | JM1 | 8 | 3.3V |
14 | JM2 | 18 | 3.3V |
14 | JM3 | 4 | 3.3V |
15 | JM2 | 48 | VCCIO15 | Supplied by the baseboard. |
15 | JM2 | 2 | VCCIO15 | Supplied by the baseboard. |
16 | JM1 | 48 | VCCIO16 | Supplied by the baseboard. |
Please refer to the Pin-out tables page for additional information.
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JTAG access to the Xilinx Artix-7 FPGA and System Controller CPLD devices is provided through B2B connector JM2.
JTAG Signal | B2B Pin |
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TMS | JM2-93 |
TDI | JM2-95 |
TDO | JM2-97 |
TCK | JM2-99 |
JTAGEN pin in B2B connector JM1 is used to select JTAG access for FPGA or SC CPLD:
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Special purpose pins are connected to System Controller CPLD and have following default configuration:
Pin Name | Mode | Function | Default Configuration |
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PGOOD |
INOUT | Power good | Active low when EN1 is low or module power is invalid |
otherwhise high impedance | |||
JTAGEN | Input | JTAG select | Low for normal operation, high for System Controller CPLD access. |
EN1 | Input | Power Enable | When forced low, pulls POR_B low to emulate power on reset. |
NOSEQ | - | No function | Not used. |
MODE | - | No function | Not used. |
Pin usages depends on Purpose of this IOs depends in the CPLD Firmware, please check also CPLD Firmware description, see: TE0712 CPLD
On-board LEDs
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The Si5338 can be programmed to change the output frequency of the FPGA clocks (the Ethernet clock must remain at 50 MHz). An I2C bus is connected between the FPGA (master) and clock generator (slave). Proper logic needs to be created in the FPGA to exercise the I2C bus with the correct data. See the reference design section for more information.
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CLK Output | FPGA Bank | FPGA Pin | IO Standard | Net Name | Default Frequency REV 01, REV 02 | Default Frequency REV 03 and higher | Notes |
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CLK0 | 35 | K4/J4 | DIFF_SSTL15 | CLK0_P/N | Off |
100MHz LVDS18 | NB! Since PCB REV02. | |
CLK1A | - | - |
CLK50M | 50 MHz | 50MHz CMOS33 | PHY chip RMII reference clock. | |
CLK1B | 34 | R4 |
CLK50M2 |
Off |
50MHz CMOS33 | NB! Since PCB REV02. | ||||||
CLK2 | 216 | F6/E6 | Auto | MGT_CLK0_P/N | 125 MHz | 125MHz LVDS18 | GTP transceiver clock. |
CLK3 | 35 | H4/G4 | DIFF_SSTL15 | PLL_CLK_P/N | 50 MHz |
50MHz LVDS18 |
Certain B2B connector pins are connected to the FPGA pins which are capable of handling clocking signals from the user’s PCB (baseboard). See schematics B2B page for additional information.
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The 10/100 Mbps Ethernet PHY TLK106 (U5) by Texas Instruments is connected to the FPGA bank 14 using Reduced Media Independent Interface standard (RMII). The RMII standard has reduced set of data lines (two rather than four) and a higher clock frequency (50 MHz rather than 25 MHz) compared to the Media Independent Interface standard (MII). A management interface is also available allowing access to registers in the PHY chip. Transmit and receive signals are connected to the B2B connector JM1. The magnetics and RJ-45 jack must be placed on the user's PCB (baseboard).
FPGA Ethernet Signals
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FPGA Pin | Signal Name | Signal Description |
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N17 | ETH-RST | Ethernet reset, active-low. |
N15 | LINK_LED | Ethernet LED pin indication mode: in mode 1 - LINK, in mode 2 - ACT. |
R16 | MDC | Ethernet management clock. |
P17 | MDIO | Ethernet management data. |
P14 | ETH_TX_D0 | Ethernet transmit data 0. Output to Ethernet PHY. |
P15 | ETH_TX_D1 | Ethernet transmit data 1. Output to Ethernet PHY. |
R14 | ETH_TX_EN | Ethernet transmit enable. |
N13 | ETH_RX_D0 | Ethernet receive data 0. Input from Ethernet PHY. |
N14 | ETH_RX_D1 | Ethernet receive data 0. Input from Ethernet PHY. |
P20 | ETH_RX_DV | Ethernet receive data valid. |
All signals are connected to the FPGA bank 14 and correspond to LVCMOS33 standard.
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It is important that all baseboard I/Os are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS181 - "Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics" for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0712 module.
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3.3Vout or 1.8Vout from the module can be used to enable power supply for variable bank power and periphery, see also 4 x 5 SoM Integration Guide#4x5SoMIntegrationGuide-4x5ModuleControllerIOs |
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Power Power Rails
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | Direction | Notes |
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VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | SoM supply voltage (from the baseboard). |
3.3VIN | 13, 15 | - | Input | SoM supply voltage (from the baseboard). |
1.5V | - | 19 | Output | Module internal 1.5V level. |
1.8V | 39 | - | Output | Module internal 1.8V level. Maximum 300mA available. |
3.3V14 | - | 10, 12 | Output | Module internal 3.3V level. |
3.3V | 14 | Output | Module internal 3.3V level. Not on all 4x5 modules | |
VCCIO13 | - | 1, 3 | Input | High-Range bank supply voltage (from the baseboard). |
VCCIO15 | - | 7, 9 | Input | High-Range bank supply voltage (from the baseboard). |
VCCIO16 | 9, 11 | - | Input | High-Range bank supply voltage (from the baseboard). |
VREF_JTAG | - | 91 | Output | JTAG reference voltage (3.3V). |
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Variants Currently In Production
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Module Variant
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Junction Temperature
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Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference Document |
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VIN supply voltage | -0.3 | 6.5 | V | EP53F8QI datasheet. |
3.3VIN supply voltage | -0.3 | 6.0 | V | TPS748 datasheet. |
HR I/O banks supply voltage (VCCO) | -0.5 | 3.6 | V | Xilinx datasheet DS181 |
HR I/O banks input voltage | -0.4 | VCCO + 0.55 | V | Xilinx datasheet DS181 |
GTP transceivers Tx/Rx input voltage | -0.5 | 1.26 | V | Xilinx datasheet DS181 |
Storage temperature | -55 | 100 | °C | See IM4G16D3EABG datasheet. |
Recommended Operating Conditions
Parameter | Min | Max | Units | Reference Document |
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VIN supply voltage | 2.4 | 5.5 | V | EP53F8QI datasheet |
Technical Specifications
Absolute Maximum Ratings
Parameter
Units
Reference Document
VIN supply voltage
V
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3.3VIN supply voltage |
2. |
9 |
5. |
5 | V | TPS748 datasheet. |
HR I/O banks supply voltage (VCCO) |
1. |
14 | 3. |
465 | V | Xilinx datasheet DS181 |
HR I/O banks input voltage | -0. |
20 |
VCCO + 0. |
2 | V | Xilinx datasheet DS181 |
Storage temperature
-55
100
°C
Recommended Operating Conditions
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Physical Dimensions
- Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
- Mating height with standard connectors: 8mm
- PCB thickness: 1.6mm
- Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.
All dimensions are shown in millimeters.
Weight
16 - 27 g, Plain module (depends on variant).
8.8 g, Set of nuts and bolts.
Currently Offered Variants
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Set correct link to the shop page overview table of the product on English and German. Example for TE0706: ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706 DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706 |
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Revision History
Hardware Revision History
Date | Revision | Notes | PCN | Documentation Link |
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2016-12-09 | 02 | Second production revision | Click to see PCN | TE0712-02 |
2013-12-02 | 01 | First production revision | TE0712-01 |
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Document Change History
Date | Revision | Contributors | Description | ||||||||||||||||||||||||||
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2022-12-22 | v.31 |
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2020-07-03 | v.23 | John Hartfiel |
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2019-01-10 | v.22 | John Hartfiel |
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2017-12-15 | v.18 | John Hartfiel |
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2017-12-12 | v.15 |
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Note |
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Assembly variants for higher storage temperature range are available on request. |
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Physical Dimensions
- Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
- Mating height with standard connectors: 8mm
- PCB thickness: 1.6mm
- Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.
All dimensions are shown in millimeters.
Weight
16 - 27 g, Plain module (depends on variant).
8.8 g, Set of nuts and bolts.
Revision History
Hardware Revision History
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Notes
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01
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First production revision
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Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Document Change History
Date | Revision | Contributors | Description | ||||||||
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Page info | modified-date | modified-date | dateFormat | yyyy-MM-ddJohn Hartfiel |
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2017-05-29 | v.13 | Jan Kumann |
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2017-03-01 | v.7 | John Hartfiel |
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2017-01-26 | v.3 | Jan Kumann |
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2017-01-20 | v.2 | Jan Kumann |
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2013-12-02 | v.1 | Antti Lukats |
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Disclaimer
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