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Refer to https://wiki.trenz-electronic.de/display/PD/TE0712+TRM for online version of this manual and the rest of available documentation.

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Trenz Electronic TE0712 is an industrial-grade FPGA module integrating a Xilinx Artix-7 FPGA, a 10/100 Mbit Ethernet transceiver, 1 GByte of DDR3 SDRAM, 32 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.
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Programmable unit
Content
Notes
Xilinx Artix-7 FPGANot programmedU1
System Controller CPLDProgrammedU3
SPI Flash OTP areaEmptyU4
SPI Flash main array
EmptyU4
SPI Flash Quad Enable bitSetU4
Microchip 11AA02E48
Globally unique EUI-48 (Ethernet MAC address)
U7
Programmable quad clock generator, Silicon Labs Si5338Programmed, CLK1A - 50M, CLK2 - 125M, CLK3 - 50MU2
Signals, Interfaces and Pins
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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
13JM110VCCIO13Supplied by the baseboard. Not available on XC7A35T assembly variant.
13JM320VCCIO13Supplied by the baseboard. Not available on XC7A35T assembly variant.
14JM183.3V
14JM2183.3V
14JM343.3V
15JM248VCCIO15Supplied by the baseboard.
15JM22VCCIO15Supplied by the baseboard.
16JM148VCCIO16Supplied by the baseboard.
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The Si5338 can be programmed to change the output frequency of the FPGA clocks (the Ethernet clock must remain at 50 MHz). An I2C bus is connected between the FPGA (master) and clock generator (slave). Proper logic needs to be created in the FPGA to exercise the I2C bus with the correct data. See the reference design section for more information.

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 CLK Output
FPGA Bank
FPGA Pin
IO Standard
Net Name
Default Frequency
REV 01, REV 02		Default Frequency
REV 03 and higher		Notes
CLK035K4/J4DIFF_SSTL15CLK0_P/NOff
--
100MHz LVDS18
NB! Since PCB REV02.
CLK1A--
 

CLK50M50 MHz
50MHz CMOS33
PHY chip RMII reference clock.
CLK1B34R4
 

CLK50M2
CLK50M2
Off
--
50MHz CMOS33
NB! Since PCB REV02.
CLK2216F6/E6AutoMGT_CLK0_P/N125 MHz
125MHz LVDS18
GTP transceiver clock.
CLK335H4/G4DIFF_SSTL15PLL_CLK_P/N50 MHz
 
50MHz LVDS18

Certain B2B connector pins are connected to the FPGA pins which are capable of handling clocking signals from the user’s PCB (baseboard). See schematics B2B page for additional information.
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The 10/100 Mbps Ethernet PHY TLK106 (U5) by Texas Instruments is connected to the FPGA bank 14 using Reduced Media Independent Interface standard (RMII). The RMII standard has reduced set of data lines (two rather than four) and a higher clock frequency (50 MHz rather than 25 MHz) compared to the Media Independent Interface standard (MII). A management interface is also available allowing access to registers in the PHY chip. Transmit and receive signals are connected to the B2B connector JM1. The magnetics and RJ-45 jack must be placed on the user's PCB (baseboard).
FPGA Ethernet Signals

 
FPGA PinSignal NameSignal Description
N17ETH-RSTEthernet reset, active-low.
N15LINK_LEDEthernet LED pin indication mode: in mode 1 - LINK, in mode 2 - ACT.
R16MDC
Ethernet management clock.
P17MDIOEthernet management data.
P14ETH_TX_D0Ethernet transmit data 0. Output to Ethernet PHY.
P15ETH_TX_D1Ethernet transmit data 1. Output to Ethernet PHY.
R14ETH_TX_ENEthernet transmit enable.
N13ETH_RX_D0Ethernet receive data 0. Input from Ethernet PHY. 
N14ETH_RX_D1Ethernet receive data 0. Input from Ethernet PHY. 
P20ETH_RX_DVEthernet receive data valid.
All signals are connected to the FPGA bank 14 and correspond to LVCMOS33 standard.
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See Xilinx datasheet DS181 - "Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics" for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0712 module.
 Info
3.
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3Vout or 1.8Vout from the module  can be used to enable  power supply for variable bank power and periphery, see also
4 x 5 SoM Integration Guide#4x5SoMIntegrationGuide-4x5ModuleControllerIOs
FAQ#PCBDesign  → Power sequencing for variable IO banks and connected periphery


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Power Rails
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Power Rails
Power Rail Name
B2B Connector JM1 Pin
B2B Connector JM2 Pin
Direction
Notes
VIN
1, 3, 52, 4, 6, 8InputSoM supply voltage (from the baseboard).
3.3VIN13, 15-InputSoM supply voltage (from the baseboard).
1.5V-19OutputModule internal 1.5V level.
1.8V
39-Output
Module internal 1.8V level. Maximum 300mA available.
3.3V -10, 12OutputModule internal 3.3V level.
3.3V14
OutputModule internal 3.3V level. Not on all 4x5 modules
VCCIO13-1, 3Input
High-Range bank supply voltage (from the baseboard).
VCCIO15-7, 9InputHigh-Range bank supply voltage (from the baseboard).
VCCIO169, 11-InputHigh-Range bank supply voltage (from the baseboard).
VREF_JTAG-91OutputJTAG reference voltage (3.3V).
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 Include Page
4 x 5 SoM LSHM B2B Connectors
4 x 5 SoM LSHM B2B Connectors
Variants Currently In Production
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Module Variant
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Junction Temperature
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Technical Specifications
Absolute Maximum Ratings
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Parameter
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Units
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Reference Document
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VIN supply voltage
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V
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Storage temperature
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-55
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100
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°C
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Recommended Operating Conditions
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Technical Specifications
Absolute Maximum Ratings
Parameter
MinMax
Units
Reference Document
VIN supply voltage
-0.36.5
V
EP53F8QI datasheet.
3.3VIN supply voltage-0.36.0VTPS748 datasheet.
HR I/O banks supply voltage (VCCO)-0.53.6VXilinx datasheet DS181
HR I/O banks input voltage-0.4 VCCO + 0.55VXilinx datasheet DS181
GTP transceivers Tx/Rx input voltage-0.51.26VXilinx datasheet DS181
Storage temperature
-55
100
°C
See IM4G16D3EABG datasheet.
Recommended Operating Conditions
ParameterMinMaxUnitsReference Document
VIN supply voltage2.45.5VEP53F8QI datasheet.
3.3VIN supply voltage2.95.5VTPS748 datasheet.
HR I/O banks supply voltage (VCCO)1.143.465VXilinx datasheet DS181
HR I/O banks input voltage-0.20VCCO + 0.2VXilinx datasheet DS181

Physical Dimensions
  • Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.
  • Mating height with standard connectors: 8mm
  • PCB thickness: 1.6mm
  • Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.
All dimensions are shown in millimeters.
 Image Added   Image Added
Weight
16 - 27 g,  Plain module (depends on variant).
8.8 g,  Set of nuts and bolts.
Currently Offered Variants 
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hiddentrue
idComments
Set correct link to the shop page overview table of the product on English and German.
Example for TE0706:
    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706
    DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

 Scroll Title
anchorTable_VCP_SO
titleTrenz Electronic Shop Overview
 Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue
Trenz shop TE0712 overview page
English pageGerman page
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
 Note
Assembly variants for higher storage temperature range are available on request.
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Physical Dimensions
  • Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.
  • Mating height with standard connectors: 8mm
  • PCB thickness: 1.6mm
  • Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.
All dimensions are shown in millimeters.
 Image Removed   Image Removed
Weight
16 - 27 g,  Plain module (depends on variant).
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Revision History
Hardware Revision History
 
DateRevision
Notes
PCNDocumentation Link
2016-12-0902Second production revisionClick to see PCNTE0712-02
2013-12-02
01
First production revision

TE0712-01
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
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Contributors
Description
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Updated Download link for this document
2022-12-22
v.31
Waldemar Hanemann 
  • Variants will changed to shop search
2020-07-03v.23John  Hartfiel
  • add power sequencing notes
2019-01-10v.22John  Hartfiel
  • Update document change history
  • Update system controller and power sequencing chapter
2017-12-15v.18John  Hartfiel
  • Update Board to Board (B2B) I/Os
2017-12-12v.15John  Hartfiel
  • Replace B2B connector section
  • Typo correction on Clocking section
2017-05-29v.13Jan Kumann
  • Variants table added.
  • Key Features section relocated.
2017-03-01v.7John Hartfiel
  • BUGFIX in the description of System Controller I/O section
  • Update Clocking Section
2017-01-26
v.3
Jan Kumann
  • New block diagram.
  • Few corrections.
2017-01-20
v.2

Jan Kumann
  • Revised version.
2013-12-02 v.1Antti Lukats
  • Work in progress.
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