VG96 connector (mounting holes and solder pads, J6) and 50-pin IDC male connector socket (J5) for access to PL I/O-bank pins
USB2.0 type A connector, or optionally Micro USB 2.0 connector
1 x RJ45 GbE MagJack (J3), connected via MDI to B2B connector JB1
1 x Marvell Alaska 88E1512 GbE PHY, providing Ethernet interface in conjunction with RJ45 GbE MagJack (J2)
4 A High-Efficiency Power SoC DC-DC Step-Down Converter (Enpirion EN6347) for 3.3V power supply
XMOD JTAG- / UART-header JX1
Micro SD card socket
SDIO port expander with voltage-level translation and jumper (J13) for selection of SDIO voltage on SoM side
DIP-switches S1 to set SoM's control signals
1 x user-push button (S2), by default configured as system reset button
3 x VCCIO selection jumper J10, J11 and J12 to set SoM's PL I/O-bank voltages
5V power supply barrel jack
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VCCIO voltage selection jumpers are all set to 1.8 V.
S2 switch configured as reset button.
One VG96 connector (not soldered to the board, but included in the package as separate component)
Different delivery configurations are available upon request.
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Table_SIP_XMODconfig
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XMOD adapter board DIP-switch positions for voltage configuration
Scroll Table Layout
orientation
portrait
sortDirection
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repeatTableHeaders
default
style
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sortByColumn
1
sortEnabled
false
cellHighlighting
true
XMOD DIP-switches
Position
Switch 1
ON
Switch 2
OFF
Switch 3
OFF
Switch 4
ON
Note
Use Xilinx AMD compatible TE0790 adapter board (designation TE-0790-xx with out 'L') to program the Xilinx AMD Zynq devices.
The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download.
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Table_SIP_ETH
title
RJ45 connectors
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
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sortByColumn
1
sortEnabled
false
cellHighlighting
true
PHY U6 pins
B2B-pin
Notes
ETH-MDC/ETH-MDIO
JB3-49, JB3-51
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PHY_LED0
-
Connected to GbE MagJack J2 LED0 (green). Also connected to J5-24 (PHY_LED0_CON).
PHY_LED1
-
Connected to GbE MagJack J2 LED1 (green). Also connected to J5-23 (PHY_LED1_CON).
PHY_INT
JB3-33
-
CONFIG
JB3-60
-
CLK125
JB3-32
PHY Clock (125 MHz) output.
ETH-RST
JB3-53
-
RGMII
JB3-31 JB3-37 - JB-44 JB3-47 JB3-57 - JB-59
Reduced Gigabit Media Independent Interface. 12 pins.
Note
ETH-RXCK is connected via 0Ohm to JB3-31 (R18)and JB3-58 (R19). Usage depends on Module and Xilinx AMD IP restrictions In case of performance problems remove 0Ohm resistor from the unused Pin.
The TE0706 Carrier Board is equipped with a Texas Instruments TXS02612 SDIO SDIO Port Expander, which is needed for voltage translation due to different voltage levels of the Micro SD Card and the PS MIO-bank of the Zynq device of the mounted SoM. The Micro SD Card has 3.3V signal voltage level, but the PS MIO-bank on the Xilinx AMD Zynq module has VCCIO of 1.8V or 3.3V depending on the attached module. This has to be selected by J13.
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The maximum power consumption of the Carrier Board depends mainly on the mounted SoM's FPGA design running on the Zynq device.
Xilinx AMD provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.