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Overview

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OnRefer to https://wikishop.trenz-electronic.de/de/display/PDDownload/?path=Trenz_Electronic/TE0714 thefor onlinedownloadable version of this manual and otheradditional technical documentsdocumentation canof bethe foundproduct.

 

The Trenz Electronic TE0714 is an industrial-grade SoM (System on Module) based on Xilinx Artix-7, 16 Mbyte MByte Flash memory and powerful switching mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. All modules in 4 x 5 cm form factor are mechanically compatible.

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  1. Xilinx Artix-7 FPGA, U4
  2. SPI Flash, U7
  3. B2B Connector, JM2
  4. B2B Connector, JM1
  5. MEMS Oscillator (PL Clock), U8
  6. Single Output Low-Dropout Linear Regulator, U6 (1.2V_MGT)
  7. Single Output Low-Dropout Linear Regulator, U5 (1.0V_MGT)
  8. Low-Jitter Precision LVDS Oscillator (GT Clock), U2
  9.  Red Indication LED,D4
  10. Step-Down DC-DC Converter, U1 (1.0V)
  11. PFET Load Switch With Configurable Slew Rate, Q1 (3.3V)
  12. Low Power Step-Down DC-DC Converter, U3 (1.8V)
  13. Voltage Detector for Circuit Initialization and Timing Supervision, U23 

Key Features

  • Xilinx Artix-7 (A15T, A35T, A50T)

  • Rugged for Sock and High Vibration
  • 16 MByte QSPI Flash Memory
  • Differential MEMS Oscillator for GT Clocking
  • MEMS Oscillator for PL Clocks (Optional)
  • Plug-On Module With 2 × 100-Pin High-Speed Hermaphroditic Strips
    • 144 FPGA I/O's (Max 68 Differential)
    • XADC Analog Input
    • 4 GTP (High-Performance Transceiver) Lanes
    • GT Reference Clock Input
    • Optimized I/O and Power Pins for Good Signal Integrity
  • On-board High-Efficiency DC-DC Converters
  • Power Supply for All On-Board Components
  • eFUSE Bit-Stream Encryption (AES)
  • One User Configurable LED

Different configurations for cost and performance optimization available upon request. Available options are:

  • FPGA Type (A15T, A35T, A50T), temperature grade
  • GT Clock Frequency (or none if not implemented)
  • PL Clock Frequency and precision (or none if not implemented)
  • Config and B14 Bank Voltage: 1.8V or 3.3V
  • SPI Flash type (or none if not implemented)
  • LED Color (or none if not implemented)
  • PUDC Pin strapping (pull high or pull down)
  • GT Power Enable pin strapping (default power enabled or disabled)

Initial Delivery State

Storage device name

Content

Notes

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor

SPI Flash Quad Enable bit

Programmed

 

SPI Flash main array

demo design

 

EFUSE USER

Not programmed

 

EFUSE Security

Not programmed

 

Signals, Interfaces and Pins

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JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1. 

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To power-up a module, power supply with minimum current capability of 1A is recommended.

Power

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Supply

TE0714 needs one single power supply with nominal of 3.3V.

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Variants Currently In Production

Module Variant

FPGA Chip Model

GT/PL Clock [MHz]PUDCGT PWR Enable

B14/Config Voltage [V]

R27 (VCCIO_0 on JM2 Pin 54)SPI Flash

LED

D4

TE0714-02-35-2IA35T-2I125/25HighEnabled3.3JM2 Pin 54 = VCCIO_0 (3.3 V)S25FL127SRed
TE0714-02-35-2IC6A35T-2I125/25HighEnabled1.8JM2 Pin 54 = OpenN25Q128Red
TE0714-02-35-2IC7A35T-2I125/25LowEnabled3.3JM2 Pin 54 = OpenS25FL127SRed
TE0714-02-50-2IA50T-2I125/25HighEnabled3.3JM2 Pin 54 = VCCIO_0 (3.3 V)S25FL127SRed
TE0714-02-50-2IC6A50T-2I125/25HighEnabled1.8JM2 Pin 54 = OpenN25Q128Red
Note

On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module.

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Parameter

MinMax

Units

Notes

Reference document

Vin VIN supply voltage

-0.1

3.6

V

  
I/O Bank supply voltage-0.53.6V Xilinx document DS181
I/O input voltage for FPGA I/O banks-0.4VCCO_X+0.55V Xilinx document DS181
GT Transceiver-0.51.26V Xilinx document DS181

Voltage on module JTAG pins

-0.4

VCCO_0+0.55

V

VCCO_0 is 1.8V or 3.3V nominalXilinx document DS181

Storage temperature

-40

+85

°C

  

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ParameterMinMaxUnitsNotesReference document
Vin VIN supply voltage3.1353.45V  
IO Bank supply voltage for I/O banks1.143.465V Xilinx document DS181
I/O input voltage for I/O banks-0.20VCCO + 0.20V Xilinx document DS181
Voltage on module JTAG pins3.1353.465VFor a module variant with
3.3V CONFIG Bank option		Xilinx document DS181

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-
 PCB Revision

Changes                                   

PCN linkDocumentation link
02VCCIO0 added to B2BPCN-20160815TE0714

01

Current Hardware Revision, no changes

-TE0714-01 TRM02VCCIO0 added to B2BPCN-20160815

Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

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