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Overview

Refer to 

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http://

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trenz

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org/tebf0808-info for 

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the current online version of this manual and 

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other 

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available documentation

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The Trenz Electronic TEBF0808 Carrier Board carrier board is a baseboard for the Xilinx Zynq Ultrascale+ MPSoC modules TE0808 and TE0803, which exposes the module's B2B connector pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ SoMs and for developing purposes.

Key Features

The carrier board has a Mini-ITX form factor making it capable to be fitted into a PC enclosure. On the PC enclosure's rear and front panel, MGT interfaces and connectors are accessible, for the front panel elements there are also Intel-PC compatible headers available. 

Key Features

• Mini-ITX form factor, PC enclosure compatible
• ATX-24 PC EnclosureATX power supply connector
• Optional 12V standard power plug
• Headers
  • Intel 10-pin HDA Audio
  • Intel 9-pin Power-/Reset-Button, Power-/HD-LED
  • PC-BEEPER
• On-board Power- / Reset-Switches
• 2x Configuration 4-bit DIP-switches
• 2x Optional 4-wire PWM fan connectors
• PCIe Slot - one PCIe lane (16 lane connector)
• CAN FD Transceiver (10 Pin IDC connector or and 6-pin header)
• 4x On-board configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x  Microchip 24AA025E48T-I/OT)
• Dual SFP+ Connector (2x1 Cage)
• One Display-Port 1x DisplayPort (single lane)
• One 1x SATA Connector
• 2x USB3.0 A Connector (Superspeed Host Port (Highspeed at USB2.0))
• 1x USB3.0 on-board header connector with two ports
• FMC HPC Slot (FMC_VADJ max. VCCIO)
• FMC Fan
• Gigabit Ethernet RGMII PHY with RJ45 MegJackMagJack
• All Carrier Board carrier board peripherals' I²C - interfaces muxed to MPSoC's I²C - interface on PS bank 503
• Quad programmable PLL clock generator SI5338A
• 2x SMA coaxial connectors for clock signals
• MicroSD- / MMC-Card Socket (bootable)
• 32 Gbit (4 GByte) on-board eMMC memory flash (8 banks a 4 Gbit)
• Two 2x System Controller CPLDs Lattice MachXO2 1200 HC
• One 1x Samtec FireFly (4 GT lanes bidirectional)
• One 1x Samtec FireFly connector for reverse loopback
• 2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLDs
• 20 Pin -pin ARM JTAG Connector (PS JTAG0)
• 3x PMOD connector (GPIO's and I²C interface to SC CPLDs / and MPSoC module
• Carrier SC CPLD managing power-up sequence of MPSoC module
• )
• On-board DCDC DC-DC PowerSoCs

Additional assembly options are available for cost or performance optimization upon request.

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Figure 1: TEBF0808-04 Block Diagram

Main Components

Image Removed

Figure 2: TEBF0808-04 Carrier Board

1. PMOD connector, P2
2. MicroSD Card socket (on bottom side), J16
3. Display Port socket, J13
4. USB3.0 A 2x , RJ45 1x (stacked), J7
5. SFP+ 2x1 cage, J14
6. PCIe x16 connector (one PCIe lane connected), J11
7. FMC HPC, J5
8. FMC-Fan connector 5V, J19
9. USB3.0 connector, J8
10. PC-BEEPER 4-pin header, J23
11. SMA coaxial connector (SI5338A clock output), J32
12. SMA coaxial connector (clock input to MPSoC module), J33
13. eMMC Card socket, J27
14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
16. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
17. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
18. CAN bus 6-pin header, J29
19. CAN bus 10-pin connector, J24
20. ARM-JTAG  20-pin connector, J30
21. ATX power supply connector, J20
22. 4-Wire PWM fan connector, J35
23. JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to MPSoC module, J12
24. JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to System Controller CPLDs, J28
25. Power Jack 2.1mm 12V, J25
26. 4x DIP-switch, S5
27. Power Button, S1
28. Samtec FireFly Connector  for reverse loopback, J21/J22
29. Samtec FireFly Connector (4 GT lanes bidirectional), J6/J15
30. SATA Header, J31
31. 4-Wire PWM fan connector, J26
32. Programmable on-module PLL I²C interface 10-pin header, J17
33. Reset Button, S2
34. INTEL HDA 9-pin header, J9
35. Intel front panel (PWR/RST/LED) 9-pin header, J10
36. Samtec FireFly Connector J6/J15 I²C interface 3-pin header, J34
37. 4x DIP-switch, S4
38. PMOD connector, P3
39. PMOD connector, P1
40. Battery Holder CR1220, B1

Initial Delivery State

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Storage device name

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Content

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Notes

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Not programmed

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Table 1: Initial Delivery State of the flash memories

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector:

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All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

For detailed information about the pin out, please refer to the Pin-out Tables. 

The configuration of the I/O's MIOx, MIOx ... MIOx, ... are depending on the base-board peripherals connected to these pins.

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TO-DO (future):
If Vivado board part files are available for this module, the standard configuration of the MIO pins by using this board part files should be mentioned here. This standard configuration of those pins are also apparent of the on-board peripherals of base-boards related to the module.
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MGT Lanes

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MGT Lanes should be separately listed, as those are more specifically not just I/O's.  
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MGT_RX4_P, MGT_RX4_N, pins J1-23, J1-21
MGT_TX4_P, MGT_TX4_N, pins J1-22, J1-20

MGT_RX5_P, MGT_RX5_N, pins J1-17, J1-15
MGT_TX5_P, MGT_TX5_N, pins J1-16, J1-14

MGT_RX6_P, MGT_RX6_N, pins J1-11, J1-9
MGT_TX6_P, MGT_TX6_N, pins J1-10, J1-8

MGT_RX7_P, MGT_RX7_N, pins J1-3, J1-5
MGT_TX7_P, MGT_TX7_N, pins J1-4, J1-6

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1 Reference clock MGT_CLK3 from programmable
quad clock generator U16 to bank's pins AA6/AA5.

1 Reference clock MGT_CLK2 from B2B connector J3
(pins J3-81, J3-83) to bank's pins W6/W5.

Block Diagram description of depicted on-board peripherals

Table 1: Description of depicted on-board peripherals

Main Components

Image Added

Figure 2: TEBF0808-04 Carrier Board

1. PMOD connector, P2
2. MicroSD Card socket (on bottom side), J16
3. DisplayPort connector, J13
4. USB3.0 A 2x , RJ45 1x (stacked), J7
5. SFP+ 2x1 cage, J14
6. PCIe x16 connector (one PCIe lane connected), J11
7. FMC HPC connector, J5
8. FMC-Fan connector 5V, J19
9. USB3.0 connector, J8
10. PC-BEEPER 4-pin header, J23
11. SMA coaxial connector (SI5338A clock output), J32
12. SMA coaxial connector (clock input to MPSoC module), J33
13. MMC Card socket, J27
14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
16. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
17. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
18. CAN bus 6-pin header, J29
19. CAN bus 10-pin connector, J24
20. ARM JTAG  20-pin connector, J30
21. ATX-24 power supply connector, J20
22. 4-Wire PWM fan connector, J35
23. JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to MPSoC module, J12
24. JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to System Controller CPLDs, J28
25. Power Jack 2.1mm 12V, J25
26. 4-bit DIP-switch, S5
27. Power Button, S1
28. Samtec FireFly connector  for reverse loopback, J21/J22
29. Samtec FireFly connector (4 GT lanes bidirectional), J6/J15
30. SATA header, J31
31. 4-Wire PWM fan connector, J26
32. I²C interface of programmable on-module PLL (10-pin header), J17
33. Reset Button, S2
34. INTEL HDA 9-pin header, J9
35. Intel front panel (PWR-/RST-Button, HD-/PWR-LED) 9-pin header, J10
36. Samtec FireFly connector J6/J15 I²C interface (3-pin header), J34
37. 4-bit DIP-switch, S4
38. PMOD connector, P3
39. PMOD connector, P1
40. Battery Holder CR1220, B1

Initial Delivery State

Table 2: Initial Delivery State of the flash memories

Signals, Interfaces and Pins

FMC HPC Connector

The FMC (FPGA Mezzanine Card) connector J5 with high pin count (HPC) provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.

The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.

Image Added

Figure 3: FMC HPC Connector

Table 3: FMC connector pin-outs of available logic banks of the MPSoC

The MGT-banks have also clock input-pins which are exposed to the FMC connector. Following MGT-lanes are available on the FMC connectors J5:

Table 4: FMC connector pin-outs of available MGT lanes of the MPSoC

The FMC connector provides pins for reference clock output to the Mezzanine module and clock input to PL banks of the MPSoC:

Table 5: FMC connector pin-outs for reference clock output

The FMC connector provides further interfaces like JTAG and I²C interfaces:

Table 6: FMC connector pin-outs of available interfaces to the System Controller CPLD

Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:

Table 7:  Available VCCIO voltages on FMC connector

MIO Bank Interfaces

The TEBF0808 carrier board provides several interfaces, which are configured on the MIO banks 500 .. 503 of the Zynq Ultrascale+ MPSoC.

Following table contains the assignment of the MIO pins to the configured interfaces:

Table 8:  MIO Assignment

Following interfaces are provided by the MIO bank of the Zynq Ultrascale+ MPSoC:

• 4x USB3.0 Superspeed ports (downward compatible to USB2.0 Highspeed)
• SDIO port with muxed MikroSD and MMC Card socket
• Gigabit Ethernet interface connected per RGMII
• eMMC interface
• Master I²C interface to on-board peripherals

The block-diagram below visualizes the interfaces of the MIO bank at the Zynq Ultrascale+ MPSoC and their associated on-board peripherals.

Image Added

Figure 4: TEBF0808 MIO Interfaces

PS GT Bank Interfaces

The PS GT Bank 505 provides beside the USB3.0 Lane also following interfaces:

• SATA (PS GT bank, MGT2 Lane)
• DisplayPort (PS GT bank, MGT3 Lane, only TX-pair routed)
• PCI Express (PS GT bank, MGT0 Lane)
  
  

Table 9:  PS GT Lane Assignment

Following block diagram shows the wiring of the MGT Lanes of the PS GT bank 505 to the particular high speed data interfaces:

Image Added

Figure 5: TEBF0808 PS GT Bank 505 Interface

Follwowing table contains a brief description of the control and status signals of PCIe interface:

Table 10: Description of MGT Connectors Control and Status Signals

MGT Interfaces SFP+ and FireFly

The TEBF0808 carrier board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) and Samtec "FireFly". This connectors are capable of data transmission rates up to 10 Gbit/s with SFP+ and 28 Gbit/s with FireFly.

Table 11:  MGT Lane Assignment

Following block diagram show the wiring of the MGT lanes to the particular interface connectors:

Image Added

Figure 6: TEBF0808 MGT Interfaces

As shown on the block diagram, the FireFly connector pair J21, J22 provides four reversed looped back MGT lanes. To test any of the on-board MGT lanes or of an extern device, 4 RX/TX differential pairs are bridged on the connector, hence the transmitted data on these MGT lanes flows back to their sources in a loop-back circuit without intentional processing or modification.

Follwowing table contains a brief description of the control and status signals of the MGT lanes incorporating SFP+ and Samtec FireFly connectors:

Table 12: Description of MGT Connectors Control and Status Signals

CAN FD Interface and PMOD Connectors

On the carrier board there is a CAN FD (CAN with Flexible Data-Rate) interface available which is accessible on the CAN headers J24 (10-pin IDC connector) or J29 (6-pin header), which are connected to the CAN FD transceiver U30.

Additionally the carrier board provides PMOD connectors with GPIO and I²C interface:

Table 13:  PMOD Pin Assignment

Image Added

Figure 7: TEBF0808 CAN Interfaces, PMOD

Intel-PC Compatible Headers and FAN Connectors

The TEBF0808 carrier board provides with its Mini-ITX form factor the possibility to encase the boa rd in a PC Enclosure. For this purpose, the board is equipped with several Intel-PC compatible headers to connect them to the PC Enclosure.

Headers are available for following PC front panel elements

• Reset Button
• Power Button
• Power LED
• Hard Disc (HD) LED
• Intel High Definition Audio (HDA) Jacks

Following table gives an overview about the particular headers and a description about their functionalities:

Table 14: PC compatible Headers

Image Added

Figure 8: TEBF0808 PC Compatible Headers

JTAG Interface

The TEBF0808 carrier board provides several JTAG interfaces to program both the System Controller CPLDs and the Zynq Ultrascale+ MPSoC.

Therefore, the board is equipped with two JTAG/UART headers, which have 'XMOD FTDI JTAG Adapter'-compatible pin-assignment. So in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM and the System Controller CPLDs can be programmed via USB interface.

The System Controller CPLDs will be programmed by the XMOD-Header J28 in a cascaded JTAG chain as visualized in Figure 9. To program the System Controller CPLDs, the JTAG interface of these devices have to be activated by DIP-switch S4-3.
The 4 GPIO/UART pins (XMOD1_A/B/E/G) of the XMOD-Header J28 are routed to the System Controller CPLD U17.

XMOD-Header J12 is designated to program the Zynq Ultrascale+ MPSoC via USB interface, the 4 GPIO/UART pins (XMOD2_A/B/E/G) of this header are routed to the System Controller CPLD U39.

Image Added

Figure 9: TEBF0808 JTAG interfaces

Further JTAG interfaces of the TEBF0808 carrier board are the ARM JTAG 20-pin IDC connector J30 and on the FMC Connector J5. This JTAG interfaces are connected to the System Controller CPLD U17, hence the logical processing and forwarding of the JTAG signals depend on the SC CPLD firmware. The documentation of the firmware of the SC CPLD U17 contains detailed information on this matter.

On-board Peripherals

System Controller CPLDs

The TEBF0808 is equipped with two System Controller CPLDs - Lattice Semiconductor LCMXO2-1200HC (MachXO2 Product Family) - with the schematic designators U17 and U39.

The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic of the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

Both System Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO, PL IO-bank pins and I²C interface. The CPLDs are connected with each other through the IO pins SC_IO0 ... SC_IO8.

The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U17 and SC CPLD U39 contains detailed information on this matter.

Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS (MIO), PL bank pins and I²C interface.

Image Added

Figure 10: TEBF0808 System Controller CPLDs

Programmable PLL Clock Generator

The TEBF0808 carrier board is equipped with a Silicon Labs I²C programmable quad PLL clock generator Si5338A (U35). It's output frequencies can be programmed by using the I²C bus with address 0x70.

A 25 MHz (U7) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.

Once running, the frequency and other parameters can be changed by programming the device using the I²C-bus connected through I²C switch U16 between the Zynq module (master) and reference clock signal generator (slave).

Table 15: Pin description of PLL clock generator Si5338A

Image Added

Figure 11: Clocking Configuration of TEBF0808 Carrier Board

Si5338 OTP can only be programmed two times, as different user configurations may required different setup, TEBF0808 is normally shipped with blank OTP.
For more information Si5338 at SiLabs.

Oscillators

The TEBF0808 carrier board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:

Table 16: Reference clock signal oscillators

High-speed USB ULPI PHY

USB PHY (U9) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U10).

Table 17: USB PHY interface connections

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U12) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U13). The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U17, pin 70.

Table 18: Ethernet PHY interface connections

8-Channel I²C Switches

All on-board and on-module peripherals with accessible I²C interface are muxed to the I²C interface of the Zynq Ultrascale+ MPSoC as master.

For this purpose, the TEBF0808 carrier board is equipped with two 8-channel I²C switches provided by TCA9548A from Texas Instruments, together creating up to 16 switched I²C channels.

Refer to the data sheet of the TCA9548A chip how to address and and transmit data to the I²C slave devices through this switches.

The I²C bus works internally on-module with reference voltage 1.8V, it is connected to the MPSoC I²C interface via PS MIO bank (pins MIO38, MIO39) configured as master.

Table 19: MIO-pin assignment of the module's I²C interface

I²C addresses for on-board slave devices are listed in the table below:

Table 20:  On-board peripherals' I²C-interfaces device slave addresses

Configuration EEPROMs

The TEBF0808 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip and all have I²C interfaces:

Table 21:  On-board configuration EEPROMs overview

4-port USB3.0 Hub

On the carrier board there are up to 4 USB3.0 Super Speed ports available, which are also downward compatible to USB2.0 High Speed ports. The USB3.0 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3.0 Hub controller U4. The pin-strap configuration option of the USB3.0 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller is also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U16.

On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank to establish the USB3.0 data lane. For the USB2.0 interface, the controller is connected to the on-board USB2.0 PHY U9. The USB2.0 PHY is connected per ULPI interface (MIO pins 52..63) to MPSoC's MIO bank.

The USB3.0 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.

CAN FD Transceiver

On-board CAN FD (Flexible Data Rate) transceiver is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.

The transceiver is connected to System Controller CPLD U17, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD U17.

eMMC Memory

The TEBF0808 carrier board is equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.

24-bit Audio Codec

For high resolution digital audio signal processing, the TEBF0808 carrier board is equipped with the Analog Devices 24-bit Audio Codec chip ADAU1761 with the schematic designator U3. The Audio Codec chip is connected to the Intel High Defintion Audio (Intel HDA) compatible 9-pin header J9 with single-ended signaling for analog stereo audio signal input and output. It supports also MIC / Jack detect. Its I²C control interface is accessible by the Zynq Ultrascale+ MPSoC through I²C switch U27.

The 24-bit Audio Codec provides numerous features and is also fully programmable with its dedicated graphical tool from the manufacturer. Refer to the data sheet of this chip for more detail information and specifications.

SDIO Port Expander

Due to the different signaling voltage levels of the MicroSD and MMC Card interfaces (3.3V) and the PS MIO bank of the Zynq Ultrascale+ MPSoC (1.8V), there is voltage-translation necessary, which is fullfilled by the SDIO port expander Texas Instruments TXS02612, U15. This IC also muxes the MikroSD and the MMC Card sockets to the SDIO port of the MPSoC, which is controlled by the signal 'SEL_SD' of the System Controller CPLD U39. The SC CPLD U39 also controls the load switches to enable the card sockets J16 and J27 and to report the card detect signal both of the sockets to the MPSoC (see schematic).

DIP-Switches

There are two 4-bit DIP-witches present on the TEBF0808 carrier board to configure options and set parameters. The following section describes the functionalities of the particular switches.

DIP-switch S4

Table below describes the functionalities of the switches of DIP-switch S4 at their single positions:

Table 22: DIP-switch S4 functionality description

DIP-switch S5

DIP-switch S5 located close to PWR push-button is connected to the two System Controller CPLDs, its functionalities depend on the current firmware of the CPLDs.

The DIP-switch is connected to SC CPLD U17 and U39 as fellows:

Table 23: DIP-switch S5 connection to SC CPLDs

The boot mode of the mounted Ultrascale+ Zynq MPSoC module will be set in current SC CPLD U39 firmware version as described in the table below:

Table 23: DIP-switch S5 boot mode selection

On-board LEDs

The TEBF0808 carrier board is equipped with several LED to signal current states and activities. The functionality of the LEDs D4 ... D7 depends on the current firmware of the SC CPLDs U17 and U39.

Table 24: On-board LEDs functionality description

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power Distribution Dependencies

All on-board voltages of the TEBF0808 are generated out of the extern applied 12V power supply.

There are following dependencies how the initial 12V power supply is distributed to the on-board DC-DC converters, which power up further DCDC converters and the particular on-board voltages:

Image Added

 Figure 12: Power Distribution Diagram

Power-On Sequence Diagram

The power-on sequence of the on-board DC-DC converters depens on the current firmware of the System Controller CPLD U39.

Following diagram visualizes the connection of the DC-DC converter control signals ('Enable', 'Power-Good') with System Controller CPLD U39, which enables the particular on-board voltages.

Image Added

Figure 13: Power-On Sequence Utilizing DCDC Converter Control Signals

The TEBF0808 carrier board manages both the power-on sequence of the mounted TE0808 / TE0803 SoM and the on-board DC-DC converters via System Controller CPLD U39.

The power-on sequence of the TE0808 / TE0803 SoM is managed by utilizing the SoM's DC-DC converter control signals ('Enable', 'Power-Good'), so the DC-DC converters of the SoM dedicated to the particular Power Domains of the Zynq Ultrascale+ MPSoC will be powerer-up in a specific sequence to meet the recommended criteria to power up the Xilinx Zynq Ultrascale+ MPSoC properly.

Core voltages and main supply voltages of the Zynq Ultrascale+ MPSoC have to reach stable state and the "Power Good"-signals of the SoM have to be asserted before other voltages like bank's I/O voltages (VCCOx) can be powered up.

It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are logically high, meaning that all on-module voltages have become stable and module is properly powered up.

Adjustable PL Bank VCCO Voltage FMC_VADJ

The carrier board VCCO voltage 'FMC_VADJ' supplying the PL IO-banks of the MPSoC is provided by DC-DC converter U8 and selectable by the pins 'FMC_VID0' ... 'FMC_VID2' of the System Controller CPLD U17.

Table 25: Bit patterns for fixed values of the FMC_VADJ voltage

Note: These pins of the DC-DC converter U8 are hard-wired to initialiy fix the voltage to 1.8V (see schematic).

Power Rails

Table 26: Power pin description of B2B Module Connector.

Table 27: Power pin description of FAN Connector

Table 28: Power pin description of FMC Connector

Table 29: Power pin description of ATX-24 Connector and Power-/HD-LED/Reset Header

Table 30: Power pin description of PMOD Connector

Table 31: Power pin description of XMOD/JTAG Connector

Table 32: Power pin description of Peripherals' Connector

B2B connectors

Technical Specifications

Absolute Maximum Ratings

Table 33: Board absolute maximum ratings.

Recommended Operating Conditions

Table 34: Board recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Extended grade: 0°C to +85°C.

The carrier board itself is capable to be operated at industrial grade temperature range.

Please check the operating temperature range of the mounted UltraSOM+ modules, which determine the relevant operating temperature range of the overall system.

Physical Dimensions

• Module size: 170 mm × 170 mm.  Please download the assembly diagram for exact numbers

• Mating height with standard connectors: 5 mm

• PCB thickness: 1.844 mm ± 10%

• Highest part on PCB: approx. 32 mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

 Image Added       Image Added

Figure 14: Board physical dimensions drawing.

Revision History

Hardware Revision History

Table 35: Board hardware revision history.

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Image Added

Figure 15: Board hardware revision number.

Document Change History

Table 36: Document change history.

Disclaimer

JTAG Interface

JTAG access to the ... is provided through B2B connector .... 

...

JTAG Signal

...

B2B Connector Pin

...

System Controller I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

...

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Quad SPI Interface

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

...

Gigabit Ethernet

On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

...

USB Interface

USB PHY is provided with ...

...

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

On-board I2C devices are connected to MIO.. and MIO.. which are configured as I2C... by default. I2C addresses for on-board devices are listed in the table below:

...

Boot Process

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.

...

MODE Signal State

...

high or open

...

SD Card

...

low or ground

...

QSPI

On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

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Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL...

Programmable PLL Clock (Phase-Locked Loop)

There is a Silicon Labs I²C programmable quad PLL clock generator Si5338A (U..) ..

...

IN1/IN2

...

CLKIN_P, CLKIN_N

...

Reference clock signal from B2B connector J3, pins J3-74, J3-76
(base board decoupling capacitors and termination resistor necessary).

...

IN3

...

reference clock signal from oscillator SiTime SiT8008BI (U21)

...

IN4/IN6

...

IN5

...

not connected

...

CLK0 A/B

...

MGTCLK1_P, MGTCLK1_N

...

Reference clock signal to MGT bank 112, pins U6/U5
(100 nF decoupling capacitors).

...

MGTCLK3_P, MGTCLK3_N

...

Reference clock signal to MGT bank 111, pins AA6/AA5
(100 nF decoupling capacitors).

Oscillators

The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

...

On-board LEDs

...

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

...

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of on board DC-DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The on-board voltages of the TE07xx SoC module will be powered-up in order of a determined sequence after the external voltages '...', '...' and '...' are available. All those power-rails can be powered up, with 3.3V power sources, also shared.

Power Distribution Dependencies

regulator dependencies and max. current.

put diagram here...

See Xilinx data sheet ... for additional information. User should also check related base board documentation when intending base board design for TE07xx module.

Power-On Sequence Diagram

The TE07xx SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DCDC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

put diagram here...

Voltage Monitor Circuit

if this circuit is fitted on module, describe it here...

Power Rails

...

Voltages on B2B-Connectors

...

B2B

...

B2B

...

B2B

...

Input / Output

...

Bank Voltages

...

Bank

...

Voltage

...

Voltage Range

...

Board to Board Connectors

...

Variants Currently In Production

...

SoC Junction Temperature

...

Technical Specifications

Absolute Maximum Ratings

...

Parameter

...

Units

...

Reference Document

...

VIN supply voltage

...

V

...

Storage temperature

...

...

°C

...

Recommended Operating Conditions

...

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Extended grade: 0°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: ... mm × ... mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: ... mm.

• PCB thickness: ... mm.

• Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

 All dimensions are given in millimeters.

 Put mechanical drawings here...

Revision History

Hardware Revision History

...

Notes

...

01

...

Prototypes

...

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Put pic of PCB silk screen here showing model and revision ...

Document Change History

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...

Date

...

Revision

...

Contributors

...

Description

...

John Hartfiel

...

-removed weight section update template version

...

2017-06-08

...

v.20

...

John Hartfiel

...

add revision number and update document change history

...

2017-05-30

...

v.1

...

Jan Kumann

...

Initial document.

...

all

...

Jan Kumann, John Hartfiel

...

Disclaimer

...

...

Table of contents

Features

• Mini-ITX form factor
• ATX Power supply connector (Important 12V only Supply Required)
• optional 12V Standard Power Plug
• USB3 with USB3 HUB
• Gigabit Ethernet RJ45
• MicroSD Card (bootable)
• eMMC (bootable)
• PCIe slot - one PCIe lane (16 Lane Connector)
• Displayport Single Lane
• One SATA Connector
• FMC HPC Slot (1.8V max VCCIO)
• Dual SFP+
• One Samtec FireFly (4 GT lanes bidir)
• One Samtec FireFly connector for reverse loopback
• Fan connectors, PC Enclosure, FMC Fan
• Intel front panel connector (PWR/RST/LED)
• Intel HDA Audio connector
• CAN FD Transceiver (10 Pin IDC Connector)
• 20 Pin ARM JTAG Connector (PS JTAG0)

PC Enclosure Rear Panel Accessible I/O

• PCIe accepting 16 Lane PCIe cards (one lane used PS GT)
• FMC HPC
• Dual SFP+
• RJ45 Gigabit Ethernet
• 2x USB3 Host
• Displayport (Single lane)
• microSD
• Two LED's
• CAN FD (using DB9 to IDC10 Cable)
• One PMOD

PC Front Panel I/O

• Reset Button
• Power Button
• Power LED
• HD LED
• Intel HDA Audio
• One USB2 HS Host port
• One USB3 SS Host port

The above I/O interfaces are accessible using standard PC front panel cables.

...

Image RemovedTEBF0808-REV2 Component Locations

TEBF0808-REV2 Component Locations

...

Table: Board Component Description

TE0808 GT Transceivers

...

GT Lane Assignment

...

GT CLK Assignment

TE0808 MIO Assignment

...

MIO Assignment

TE0808 Si5345 PLL Settings

...

Recommended/Default settings for the Si5345

FMC Slot

FMC Slot is fitted as full FMC HPC.

Note: FMC VADJ maximum voltage is 1.8V (as HP banks do not support more than 1.8V).

...

Optional FAN can be mounted below the FMC slot. Ther are no components below the FMC card, so FMC cards with extended component heights can be used.

I2C Buses

...

1

...

4

...

List of I2C buses and devices (bus numbers as enumerated by Linux).

To init Si5345 use command

si534x /dev/i2c-13 0x69

DIP Switches

There are two 4 bit DIP Switches on the TEBF0808, they must be used to select some options. On TEBF0808-02 default CPLD-Firmware selects boot from SD-Card, Firmware update is needed for Boot-Mode selection.

...

DIP Switch S5 located close to PWR push-button. This DIP Switch is connected to the two baseboard control CPLD's.

...

DIP Switch S4 located close to PCIe slot.

LEDs

...

Power

ATX Power is supported but special 12V ATX power supply must be used.

System controller RGPIO 

Master CPLD Read

...

Bit

...

Master CPLD Write

...

Bit

...

Slave CPLD Read

...

Bit

...

Slave CPLD Write

...

Bit

...

PCB Revisions

Revision 02

Known Issues:

...

Revision 03