Page History
...
Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-02-10 | Thorsten Trenz | Corrected PLL initial delivery state | |
| 2017-01-25 | V55
| Jan Kumann | New block diagram. |
| 2017-01-14 | V50 | Jan Kumann | Product revision 04 images added. Formatting changes and small corrections. |
| 2016-11-15 | V45 | Thorsten Trenz | Added B2B Connector section. |
| 2016-10-18 | V40 | Ali Naseri | Added table "power rails". |
| 2016-06-28 | V38
| Thorsten Trenz, Emmanuel Vassilakis, Jan Kumann | New overall document layout with shorter table of contents. Revision 01 PCB pictures replaced with the revision 03 ones. Fixed link to Master Pin-out Table. New default MIO mapping table design. Revised Power-on section. Added links to related Xilinx online documents. Physical dimensions pictures revised. Revision number picture with explanation added. |
| 2016-04-27 | V33 | Thorsten Trenz, Emmanuel Vassilakis | Added table "Recommended Operating Conditions". Storage Temperature edited. |
| 2016-03-31 | V10 | Philipp Bernhardt, Antti Lukats | Initial version. |
...
Overview
Content Tools