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Overview
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Refer to "https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0745" for downloadable version of this manual and the rest of available documentation. |
The Trenz Electronic TE0745 is an industrial-grade SoC module integrating a Xilinx Zynq-7 (Z-7030, Z-7035 or Z-7045), 1 GByte DDR3/L SDRAM, 32 MByte SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips.
Block Diagram
Figure 1: TE0745-02 Block Diagram
Main Components
Figure 2: TE0745-02 SoC module
- Xilinx ZYNQ-7000 family SoC, U1
- 256 Mbit Quad SPI Flash Memory Micron N25Q256A, U12
- Reference clock signal oscillator SiTime SiT8008BI @33.333 MHz, U12
- Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U9
- Marvell Alaska 88E1512 Gigabit Ethernet PHY, U3
- Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16 Bit Word-Width), U3
- TI TPS51206 DDR3 Memory Termination Regulator with buffered reference votlage VTTREF, U18
- Intersil ISL12020MIRZ Real-Time-Clock, U24
- TI TCA9517 Level-shifting I²C bus repeater, U17
- LED D2 red
- LED D1 green
- Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16 Bit Word-Width), U5
- Altera Enpirion EN63A0QI 12A DCDC PowerSoC @1.0V (VCCINT), U4
- TI TPS74401RGW LDO DC/DC regulator @1.2V (MGTAVTT), U8
- TI TPS72018DRVR LDO DC/DC regulator @1.8V (MGTAUX), U6
- TI TPS74401RGW LDO DC/DC regulator @1.0V (MGTAVCC), U11
- Silicon Labs Si5338A I²C Programmable Quad Clock Generator, U13
- Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U21
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J3
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J1
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J2
- 256 Mbit Quad SPI Flash Memory (Micron N25Q256A, U14
- Microchip USB3320 USB Transceiver PHY , U32
- Reference clock signal oscillator SiTime SiT8008BI @52.000 MHz, U33
- Microchip 24AA025E48 EEPROM for MAC Address
- Lattice Semiconductor MachXO2-256HC System Controller CPLD, U2
Key Features
Industrial-grade Xilinx Zynq-7000 (Z-7030, Z-7035, Z-7045) SoM
- Rugged for shock and high vibration
- 10/100/1000 Mbps Ethernet transceiver PHY
- EEPROM for storing Ethernet MAC Address
- 16-Bit wide 1GB DDR3 SDRAM
- 32 MByte QSPI flash memory
- Programmable clock generator
- Plug-on module with 3 × 160-pin high-speed hermaphroditic strips
- 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on B2B connectors
- 8 GTX (high-performance transceiver) lanes (Z-7030: 4 GTX lanes)
- USB 2.0 OTG high-speed PHY
- On-board high-efficiency DC-DC converters
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- User LED
- Evenly-spread supply pins for good signal integrity
Additional assembly options are available for cost or performance optimization upon request.
Initial Delivery State
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Storage device name
...
Content
...
Notes
...
24AA025E48 EEPROM
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User content not programmed
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SPI Flash OTP Area
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Empty, not programmed
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Except serial number programmed by flash vendor.
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SPI Flash Quad Enable bit
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Programmed
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SPI Flash main array
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Demo design
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eFUSE USER
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Not programmed
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eFUSE Security
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Not programmed
...
Table 1: Initial delivery state
Signals, Interfaces and Pins
Board to Board (B2B) I/O's
The Board to Board connectors are high-speed hermaphroditic stacking strips and provide a modular interface to the SoC's PL and PS I/O's.
The connector supports single ended and differential signaling as the I/O's are usable as LVDS-pairs.
The I/O signals are routed from the SoC's PL banks as LVDS-pairs to the B2B connector.
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Table 2: B2B connector pin-outs of available PL and PS banks of the SoC module
For detailed information about the pin out, please refer to the Pin-out Table.
MGT lanes
The B2B connector J1 and J2 provide also access to the MGT-banks of the SoC module. There are 8 high-speed data links (Xilinx GTX transceiver) available composed as differential signaling pairs for both directions (RX/TX), means from module to base-board and vice versa.
The MGT-banks have also clock input-pins which are exposed to the B2B connector J3. Following MGT-lanes are available on the B2B connectors:
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1 reference clock signal (MGT_CLK3) from programmable quad PLL clock generator U16 to bank's pins AA6/AA5.
1 reference clock signal (MGT_CLK2) from B2B connector J3 (pins J3-81/J3-83) to bank's pins W6/W5.
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1 reference clock signal (MGT_CLK1) from programmable quad PLL clock generator U16 to bank's pins U6/U5.
1 reference clock signal (MGT_CLK0) from B2B connector J3 (pins J3-75/J3-77) to bank's pins R6/R5.
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Table 3: B2B connector pin-outs of available MGT-lanes of the SoC module
Interface on B2B connectors
The B2B connector provides further interfaces like 'JTAG' and 'I²C' to the System Controller CPLD:
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TMS, pin J1-144
TDI, pin J1-142
TDO, pin J1-145
TCK, pin J1-143
JTAG_EN, pin J1-148
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Note |
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JTAG_EN pin in B2B connector J1-148 should be kept low or grounded for normal operation! |
At normal operation the JTAG-signals will be forwarded to the SoC module. Else the JTAG_EN pin must be high or open to update the CPLD firmware via JTAG-interface.
VCCIO: PS_3.3V
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I2C_33_SCL, pin J2-119
I2C_33_SDA, pin J2-121
RTC, U24
SC CPLD, U2
MAC Address EEPROM, U23
Zynq-module, U1
Quad programmable PLL clock generator, U16
...
The I²C-interface of the RTC U24 (pin 12: SCL, pin 11: SDA) and the B2B-connector J2 are operating with the reference voltage PS_3.3V.
Following component's I²C-interfaces are operating with the reference voltage PS_1.8V (voltage level shifting 3.3V ↔ 1.8V via I²C bus repeater U17):
SC CPLD U2, bank 2, pins 16 (SDA), 17 (SCL)
MAC Address EEPROM U23, pins 1 (SCL), 3 (SDA)
Zynq-chip U1, bank 500 (MIO0), pins A25 (SCL), B26 (SDA)
Quad programmable PLL clock generator U16: pins 12 (SCL), 19 (SDA)
Component's I²C Addresses:
RTC: 0x6F
RTC RAM: 0x57
MAC Address EEPROM: 0x53
Quad programmable PLL clock generator: 0x70
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Table 4: B2B connector pin-outs of available interfaces
Default MIO Mapping
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user I/O on B2B
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Table 5: Default MIO Mapping
Gigabit Ethernet Interface
On board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U9), the 125MHz output clock is available on B2B connector J2, pin J2-150.
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Table 6: Ethernet PHY interface connections
MAC Address EEPROM
A Microchip 24AA025E48 EEPROM (U23) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I²C slave address 0x53.
USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 25 MHz oscillator (U15).
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Table 7: USB PHY interface connections
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
RTC - Real Time Clock
An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD on bank 3, pin 4.
LEDs
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D1
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Green
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D2
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Red
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Zynq-Chip (U1), bank 0 (config bank), 'DONE' (pin W9)
...
Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured.
This LED will not operate if the SC CPLD can not power up the PL supply voltage.
Table 8: LEDs of the SoC module
Boot Modes
The Zynq-module TE0745 supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.
The current boot mode will be set by the MIO0 pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'.
Following table describes how to set the control lines to configure the desired boot mode:
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MIO3
...
JTAG
...
Table 9: Selectable boot modes
System Controller CPLD
The System Controller CPLD is the central system management unit that provides numerous interfaces between the on-board peripherals and to the FPGA-module. The signals routed to the CPLD will be linked by the logic implemented in the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. So some interfaces between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence, the proper programing of the FPGA-module and to display its programming state.
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Table 10: VCCIO voltages of CPLD banks
Following table describes the interfaces and functionalities established by the CPLD, which weren't discussed elsewhere in this TRM:
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FPGA_IIC_SDA, pin 24
FPGA_IIC_SCL, pin 25
FPGA_IIC_OE, pin 19
...
FPGA bank 16, pin V29
FPGA bank 16, pin W29
FPGA bank 16, pin W26
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VCCIO: 1V8
all lines 1V8 pulled-up
Following I²C-interfaces of are linked to the I²C-lines of 'FPGA_IIC' for data-transmission between the FPGA-module and on-board peripherals:
- FMC connector J2
- PCIe connector J1
- DC/DC converter U3 and U4 (LT LTM4676)
- Quad programmable PLL clock generator U13
Note: 'FPGA_IIC_OE' must kept high for I²C-operation.
For I²C-addresses refer to the data sheets of the components.
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user I/O's
external LVDS-pairs
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10 I/O's
5 x differential signaling pairs
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EX0_P ... EX4_P
EX0_N ... EX4_N
...
pins can also be used for single-ended signaling
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user I/O's
internal LVDS-pairs
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13 I/O's
6 x differential signaling pairs
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FEX0_P ... FEX5_P
FEX0_N ... FEX5_N
FEX_DIR (single-ended I/O)
...
VCCIO: 1V8
pins can also be used for single-ended signaling
FPGA bank 18 has also reference clock input from FMC connector (CLK2, CLK3) and from clock synthesizer U9 (FCLK)
internal signal assignment:
'FEX_DIR' <= 'FMC_PRSNT_M2C_L'
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DONE, pin 7
PROGRAM_B, pin 8
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FPGA bank 0, pin V8
FPGA bank 0, pin U8
...
PLL_SCL, pin 14
PLL_SDA, pin 15
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U13, pin 12
U13, pin 19
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VCCIO: 1V8
only 'PLL_SDA' 1V8 pulled-up
...
F1SENSE, pin 99
F1PWM, pin 98
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J4-3 (low-active signal)
J4-4
...
internal signal assignment:
'FEX_5_P' <= 'F1SENSE'
'FEX_5_N' => 'F1PWM'
...
fast blinking, if FPGA not programmed
internal signal assignment:
'LED1' <= 'Button S2' or 'FEX0_P'
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PCIe control line RESET_B
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internal signal assignment:
'FEX_4_N' <= 'PCIE_RSTB'
...
Control Interface to clock synthesizer U9 (TI LMK04828B)
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SPI (3 I/O's),
4 I/O's
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CLK_SYNTH_SDIO, pin 75
CLK_SYNTH_SCK, pin 74
CLK_SYNTH_RESET, pin 54
CLK_SYNTH_CS, pin 53
CLK_SYNTH_SYNC, pin 52
LMK_STAT0, pin 62
LMK_STAT1, pin 63
...
U9, pin 20
U9, pin 19
U9, pin 5
U9, pin 18
U9, pin 6
U9, pin 31
U9, pin 48
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'CLK_SYNTH_SDIO' 3V3PCI pulled-up
internal signal assignment:
'LMK_SCK' <= 'FEX_1_P'
'LMK_SDIO' <= 'FEX_1_N'
'LMK_CS' <= 'FEX_3_P'
'LMK_SYNC' <= 'FEX_3_N'
LMK_RESET <= 'FEX_4_P'
'FEX_2_P' => 'LMK_SDIO' (FEX_2_N must be 0)
'LMK_STAT0' and 'LMK_STAT1' signals will not be evaluated.
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I²C (2 I/O's),
2 I/O's
...
LTM_SCL, pin 67
LTM_SDA, pin 66
LTM1_ALERT, pin 65
LTM2_ALERT, pin 64
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U4, pin E6 and U3, pin E6
U4, pin D6 and U3, pin D6
U4, pin E5
U3, pin E5
...
all lines 3V3 pulled-up
LTM I²C-interface also accessible trough header J10
LTM1- and LTM2-Alert signals will not be evaluated.
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EN_1V8, pin 58
PG_1V8, pin 59
EN_FMC_VADJ, pin 60
PG_FMC_VADJ, pin 61
EN_3V3, pin 51
PG_3V3, pin 57
...
U20, pin 27
U20, pin 28
U7, pin 27
U7, pin 28
U15, pin 27
U15, pin 28
...
The effective sequencing of the supply voltages depends on the currently programmed CPLD firmware.
EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously at start-up.
PG-signals will not be evaluated.
Table 11: System Controller CPLD functionalities
Clocking
The TEC0330 FPGA board has a sophisticated clock generation and conditioning system to meet the requirements of the Xilinx Virtex-7 GTH units with data transmission rates up to 13.1 Gb/s.
Clock sources
Clocking
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PS CLK
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33.3333 MHz
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U11
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PS_CLK
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PS subsystem main clock.
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ETH PHY reference
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25 MHz
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U9
...
-
...
USB PHY reference
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52 MHz
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U15
...
-
...
PLL reference
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25 MHz
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U18
...
-
...
GT REFCLK0
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-
...
B2B
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U9/V9
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Externally supplied from baseboard.
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GT REFCLK1
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125 MHz
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U10 Si5338
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U5/V5
...
Default clock is 125 MHz.
PLL - Phase-Locked Loop
There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70.
PLL connection
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IN1/IN2
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Externally supplied
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Needs decoupling on base board.
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IN3
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25MHz
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Fixed input clock.
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IN4
...
-
...
-
...
IN5/IN6
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125MHz
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Ethernet PHY output clock.
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CLK0
...
-
...
Not used, disabled.
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CLK1
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-
...
Not used, disabled.
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CLK2 A/B
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125MHz
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MGT reference clock 1.
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CLK3A
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-
...
Bank 34 clock input, default disabled, User clock.
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CLK3B
...
-
...
Not used, disabled.
Power and Power-On Sequence
Warning |
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TE0715-xx-30 has several HP banks on B2B connectors. Those banks have maximum voltage tolerance of 1.8V. Please check special instructions for the baseboard to be used with TE0715-xx-30. |
Power Supply
Power supply with minimum current capability of 3A for system startup is recommended.
Power Consumption
Power Input Pin | Max Current |
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VIN | TBD* |
3.3VIN | TBD* |
* TBD - To Be Determined soon with reference design setup.
Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise due to the DC-DC converter efficiency (it decreases when VIN/VOUT ratio rises). Typical module power consumption is between 2-3W.
Power-On Sequence
For highest efficiency of on board DC/DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.
It is important that all baseboard I/Os are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 module.
Power Rails
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Voltages on B2B
Connectors
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B2B JM1 Pin
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B2B JM2-Pin
...
Input/
Output
...
TE0715-xx-15: high range bank voltage.
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TE0715-xx-15: high range bank voltage.
...
Bank Voltages
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Bank
...
Voltage
...
TE0715-xx-15
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TE0715-xx-30
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B2B connectors
...
Technical Specifications
Absolute Maximum Ratings
...
Parameter
...
Units
...
Notes
...
VIN supply voltage
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-0.3
...
6.0
...
V
...
3.3VIN supply voltage
...
-0.4
...
3.6
...
V
...
PL IO bank supply voltage for HP I/O banks (VCCO)
...
Voltage on module JTAG pins
...
-0.4
...
V
...
Storage temperature
...
-40
...
+85
...
°C
...
Note |
---|
Assembly variants for higher storage temperature range are available on request. |
Note |
---|
Please check Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for complete list of absolute maximum and recommended operating ratings. |
Recommended Operating Conditions
...
PL I/O bank supply voltage for HR
I/O banks (VCCO)
...
PL I/O bank supply voltage for HP
I/O banks (VCCO)
...
TE0715-xx-15 does not have
HP banks
...
Xilinx datasheet DS191
or DS187
...
TE0715-xx-15 does not have
HP banks
(*) Check datasheet
...
Absolute Maximum Ratings
Recommended Operating Conditions
Physical Dimensions
Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
All dimensions are given in millimeters.
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Weight
.. g - Plain module
.. g - Set of bolts and nuts
Revision History
Hardware Revision History
...
Notes
...
Hardware revision number is written on the PCB board together with the module model number separated by the dash.
Document Change History
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Revision
...