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Overview
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Refer to "https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0745" for downloadable version of this manual and the rest of available documentation. |
The Trenz Electronic TE0745 is an industrial-grade SoC module integrating a Xilinx Zynq-7 (Z-7030, Z-7035 or Z-7045), 1 GByte DDR3/L SDRAM, 32 MByte SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips.
Key Features
Industrial-grade Xilinx Zynq-7000 (Z-7030, Z-7035, Z-7045) SoC module
- Rugged for shock and high vibration
- 10/100/1000 Mbps Ethernet transceiver PHY
- EEPROM for storing Ethernet MAC Address
- 16-Bit wide 1GB DDR3 SDRAM
- 32 MByte QSPI flash memory
- Programmable clock generator
- Plug-on module with 3 × 160-pin high-speed hermaphroditic strips
- 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on B2B connectors
- 8 GTX (high-performance transceiver) lanes
- USB 2.0 OTG high-speed PHY
- On-board high-efficiency DC-DC converters
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- User LED
- Evenly-spread supply pins for good signal integrity
Additional assembly options are available for cost or performance optimization upon request.
Block Diagram
Figure 1: TE0745-02 Block Diagram
Main Components
Figure 2: TE0745-02 SoC module
- Xilinx ZYNQ-7000 family SoC, U1
- 256 Mbit Quad SPI Flash memory Micron N25Q256A, U12
- Reference clock signal oscillator SiTime SiT8008BI @33.333 MHz, U12
- Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U9
- Marvell Alaska 88E1512 Gigabit Ethernet PHY, U3
- Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16-bit word width), U3
- TI TPS51206 DDR3 memory termination regulator with buffered reference voltage VTTREF, U18
- Intersil ISL12020MIRZ Real-Time-Clock, U24
- TI TCA9517 level-shifting I2C bus repeater, U17
- Red LED, D2
- Green LED, D1
- Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 banks a 32 MWords, 16 Bit Word-Width), U5
- Altera Enpirion EN63A0QI 12A DC-DC PowerSoC @1.0V (VCCINT), U4
- TI TPS74401RGW LDO DC-DC regulator @1.2V (MGTAVTT), U8
- TI TPS72018DRVR LDO DC-DC regulator @1.8V (MGTAUX), U6
- TI TPS74401RGW LDO DC-DC regulator @1.0V (MGTAVCC), U11
- Silicon Labs Si5338A I2C Programmable Quad Clock Generator, U13
- Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U21
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J3
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J1
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J2
- 256 Mbit Quad SPI Flash memory (Micron N25Q256A, U14
- Microchip USB3320 USB transceiver PHY , U32
- Reference clock signal oscillator SiTime SiT8008BI @52.000 MHz, U33
- Microchip 24AA025E48 EEPROM for MAC address, U23
- Lattice Semiconductor MachXO2-256HC System Controller CPLD, U2
Initial Delivery State
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Storage device name
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Content
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Notes
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24AA025E48 EEPROM
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User content not programmed
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SPI Flash OTP Area
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Empty, not programmed
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Except serial number programmed by flash vendor.
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SPI Flash Quad Enable bit
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Programmed
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SPI Flash main array
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Demo design
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eFUSE USER
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Not programmed
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eFUSE Security
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Not programmed
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Table 1: Initial delivery state
Signals, Interfaces and Pins
Board to Board (B2B) I/O's
The Board to Board connectors are high-speed hermaphroditic stacking strips and provide a modular interface to the SoC's PL and PS I/O's.
The connector supports single ended and differential signaling as the I/O's are usable as LVDS pairs.
The I/O signals are routed from the SoC's PL banks as LVDS pairs to the B2B connectors.
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Table 2: B2B connector pin-outs of available PL and PS banks of the SoC module
For detailed information about the pin out, please refer to the Pin-out Table.
MGT lanes
The B2B connector J1 and J2 provide also access to the MGT banks of the SoC module. There are 8 high-speed data lanes (Xilinx GTX transceiver) available composed as differential signaling pairs for both directions (RX/TX).
The MGT banks have also clock input-pins which are exposed to the B2B connector J3. Following MGT lanes are available on the B2B connectors:
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MGT_RX4_P, MGT_RX4_N, pins J1-23, J1-21
MGT_TX4_P, MGT_TX4_N, pins J1-22, J1-20
MGT_RX5_P, MGT_RX5_N, pins J1-17, J1-15
MGT_TX5_P, MGT_TX5_N, pins J1-16, J1-14
MGT_RX6_P, MGT_RX6_N, pins J1-11, J1-9
MGT_TX6_P, MGT_TX6_N, pins J1-10, J1-8
MGT_RX7_P, MGT_RX7_N, pins J1-3, J1-5
MGT_TX7_P, MGT_TX7_N, pins J1-4, J1-6
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1 reference clock signal (MGT_CLK3) from programmable
quad PLL clock generator U16 to bank's pins AA6/AA5.
1 reference clock signal (MGT_CLK2) from B2B connector
J3 (pins J3-81/J3-83) to bank's pins W6/W5.
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MGT_RX3_P, MGT_RX3_N, pins J3-68, J3-70
MGT_TX3_P, MGT_TX3_N, pins J3-69, J3-71
MGT_RX2_P, MGT_RX2_N, pins J3-62, J3-64
MGT_TX2_P, MGT_TX2_N, pins J3-63, J3-65
MGT_RX1_P, MGT_RX1_N, pins J3-56, J3-58
MGT_TX1_P, MGT_TX1_N, pins J3-57, J3-59
MGT_RX0_P, MGT_RX0_N, pins J3-50, J3-52
MGT_TX0_P, MGT_TX0_N, pins J3-51, J3-53
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1 reference clock signal (MGT_CLK1) from programmable
quad PLL clock generator U16 to bank's pins U6/U5.
1 reference clock signal (MGT_CLK0) from B2B connector
J3 (pins J3-75/J3-77) to bank's pins R6/R5.
Table 3: B2B connector pin-outs of available MGT lanes of the SoC module
JTAG Interface
JTAG access is provided through the SoC's PS configuration bank 0 and available on B2B connector J1.
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Table 4: B2B connector pin-out of JTAG interface
System Controller I/O Pins
Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:
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Note |
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JTAG_EN pin in B2B connector J1-148 should be kept low or grounded for normal operation! |
At normal operation the JTAG signals will be forwarded to the SoC module.
Else the JTAG_EN pin must be high or open to update the CPLD firmware via JTAG interface.
VCCIO: PS_3.3V
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Control line which sets in conjunction with signal 'BOOTMODE1' (B2B-pin J2-133)
the boot source of the Zynq chip. See section "Boot Modes".
Permanent logic high in standard SC-CPLD firmware.
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Low active Enable-signal for activating PL supply voltage.
Permanent logic high in standard SC-CPLD firmware.
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Table 5: B2B connector pin-out of SC CPLD I/O-pins
On-board LEDs
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D1
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Green
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D2
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Red
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Zynq-Chip (U1), bank 0 (config bank), 'DONE' (pin W9)
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Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured.
This LED will not operate if the SC CPLD can not power up the PL supply voltage.
Table 6: LEDs of the module
Clocking
The SoC module has the following sources to be provided with extern reference clock signals and on-board clock oscillators:
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CLKIN_N, CLKIN_P
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MGT_CLK0_P, MGT_CLK0_N
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SiTime SiT8008BI oscillator, U12
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Table 7: Clock sources overview
Default MIO Mapping
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user I/O on B2B
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Table 8: Default MIO Mapping
Gigabit Ethernet Interface
On board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U9), the 125MHz output clock is available on B2B connector J2, pin J2-150.
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PHY_LED0: J2-144
PHY_LED1: J2-146
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Table 9: Ethernet PHY interface connections
USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 25 MHz oscillator (U15).
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Table 10: USB PHY interface connections
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
I2C Interface
The I²C-interface on the B2B-connector J2 with the pins J2-119 (I2C_33_SCL) and J2-121 (I2C_33_SDA) is operating with the reference voltage PS_3.3V.
Except the RTC, the remaining component's I²C-interfaces are operating with the reference voltage PS_1.8V (voltage level shifting 3.3V ↔ 1.8V via I²C bus repeater U17).
I2C addresses for on-board devices are listed in the table below:
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Table 11: Module's I²C-interfaces overview
Boot Process
TE0745 module supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.
The current boot mode will be set by the MIO pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'.
Following table describes how to set the control lines to configure the desired boot mode:
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MIO3
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JTAG
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Table 12: Selectable boot modes
On-board Peripherals
Flash
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MAC Address EEPROM
A Microchip 24AA025E48 EEPROM (U23) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I²C slave address 0x53.
RTC - Real Time Clock
An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD on bank 3, pin 4.
Programmable PLL Clock (Phase-Locked Loop)
There is a Silicon Labs I²C programmable quad PLL clock generator Si5338A (U16) on-board. It's output frequencies can be programmed by using the I²C-bus with address 0x70.
A 25 MHz (U21) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.
Once running, the frequency and other parameters can be changed by programming the device using the I²C-bus connected between the Zynq module (master) and reference clock signal generator (slave).
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IN1/IN2
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CLKIN_P, CLKIN_N
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reference clock signal from B2B connector J3, pin J3-74/J3-76
(base board decoupling capacitors and termination resistor necessary)
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IN3
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reference clock signal from oscillator SiTime SiT8008BI (U21)
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IN4/IN6
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IN5
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not connected
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CLK0 A/B
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MGTCLK1_P, MGTCLK1_N
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reference clock signal to MGT bank 112, pin U6/U5
(100 nF decoupling capacitors)
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CLK1 A/B
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clock signal routed to B2B connector, pin J3-80/J3-82
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CLK2 A/B
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clock signal routed to B2B connector, pin J3-86/J3-88
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MGTCLK3_P, MGTCLK3_N
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reference clock signal to MGT bank 111, pin AA6/AA5
(100 nF decoupling capacitors)
Table 13: Pin description of PLL clock generator Si5338A
Power and Power-On Sequence
Power Supply
Power supply with minimum current capability of 3A for system startup is recommended.
Power Consumption
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Table 14: Maximum current of power supplies. *to be determined soon with reference design setup.
For the lowest power consumption and highest efficiency of on board DC/DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
Power-On Sequence
The on-board voltages of the TE0745 SoC module will be powered-up in order of a determined sequence after the external voltages 'PL_VIN', 'PS_VIN' and 'PS_3.3V' are available.
Warning |
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To avoid any damage to the SoC module, check for stabilized on-board voltages in steady state before powering up the SoC's I/O bank voltages VCCO_x. |
Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.
It is important that all baseboard I/Os are 3-stated at power-on until the "Power Good"-signals 'PWR_PS_OK' (J2-139) and 'PWR_PL_OK' (J2-135) are high, meaning that all on-module voltages have become stable and module is properly powered up.
Following diagram clarifies the sequence of enabling the particular on-board voltages:
Figure 3: Power-up sequence diagram
See Xilinx datasheet DS191 for additional information. User should also check related base board documentation when intending base board design for TE0745 module.
Power Rails
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Voltages on B2B
Connectors
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B2B J1 Pin
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B2B J2 Pin
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Input/
Output
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147, 149, 151, 153,
155, 157, 159
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Table 15: Power rails of the SoC module on accessible connectors
Bank Voltages
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Bank
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Voltage
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Voltage Range
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PL_1.8V if R67 is equipped
PS_1.8V if R68 is equipped
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Table 16: Range of SoC module's bank voltages
B2B connectors
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Variants Currently In Production
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SoC Junction Temperature
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Table 17: Differences between variants of Module TE0808-04
Technical Specification
Absolute Maximum Ratings
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Parameter
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Units
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Notes
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3.3V nominal ± 5%
Attention: PS_3.3V is directly connected to numerous
on-board peripherals as supply and I/O voltage.
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PL IO bank supply voltage for HP
I/O banks (VCCO)
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Voltage on module JTAG pins
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V
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Storage temperature
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-40
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+85
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°C
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Note |
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Assembly variants for higher storage temperature range are available on request. |
Recommended Operating Conditions
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PL I/O bank supply voltage for HR
I/O banks (VCCO)
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PL I/O bank supply voltage for HP
I/O banks (VCCO)
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Xilinx datasheet DS191
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-
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Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Note |
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Please check Xilinx datasheet DS191 (for XC7Z030) for complete list of absolute maximum and recommended operating ratings. |
Physical Dimensions
Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
All dimensions are given in millimeters.
Figure 4: Physical dimensions of the TE0745 SoC module
Weight
24 g - Plain module
Revision History
Hardware Revision History
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Notes
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Hardware revision number is written on the PCB board together with the module model number separated by the dash.
Figure 5: TE0745 module revision number
Document Change History
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Revision
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