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Refer to https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/TEC0330/REV03 for downloadable version of this manual and additional technical documentation of the product. |
The Trenz Electronic TEC0330 FPGA board has a PCI Express card form factor and is containing the Xilinx FPGA-module Virtex-7 XC7VX330T. This high-end FPGA-module is optimized for system performance and is used in applications with high demands on system resources.
This board is designed to fit in computing systems with PCI Express x8 slots (PCIe 2.0 or higher) and has also a SO-DIMM socket to extend the board with DDR3-RAM.
The FMC (FPGA Mezzanine Card) connector provides an high pin count (HPC) and is as an ANSI/VITA 57.1 standard a modular interface to the FPGA for mezzanine expansion cards. Further connectors provide JTAG-interfaces to the FPGA-module and to the on-board System Controller CPLD together with access to high-speed data lanes composed of differential signaling pairs.
Block Diagram
Figure 1: TEC0330-03 Block Diagram
Main Components
Figure 2: FPGA board TEC0330-03
TEC0330-03:
- PCIe x8 connector J1
- FPGA JTAG connector J9
- User button S2
- SO-DIMM socket U2
- Xilinx Virtex-7 XC7VX330T-2FFG1157C FPGA-module U1
- ANSI/VITA 57.1 compliant FMC HPC Connector J2
- SMA coaxial connector for external clock input J3
- CPLD JTAG connector J8
- I²C-connector for LT LTM4676 Step-down DC/DC regulator J10
- IDC header for access to 5 x high-speed data lanes (LVDS-pairs) J7
- 4-Wire PWM fan connector J4
- 6-pin 12V power connector J5
- Reference clock generator (RAKON P5146, U11) @10.0 MHz
- LDO DC/DC regulator (TI TPS74901RGWR, U21) @3.3V (LMK_3V3)
- 256 Mbit Quad SPI Flash Memory (Micron N25Q256A, U12)
- Cooling fan 5VDC M1 (45X5MM, 0.7W, 1.06CFM)
- System Controller CPLD (Lattice Semiconductor MachXO2-1200HC, U5)
- Ultra low jitter clock synthesizer (TI LMK04828B, U9)
- Step-down DC/DC regulator (LT LTM4676, U4) @1.0V
- Step-down DC/DC regulator (LT LTM4676, U3) @1.5V (VCC1V5), @4.0V
- I²C Programmable Quad Clock Generator (Silicon Labs Si5338A, U13)
- 4A PowerSoC DC-DC converter (Altera EN6347QI, U20) @1.8V
- LDO DC/DC regulator (TI TPS74401RGW, U18) @1.0V (MGTAVCC_FPGA)
- LDO DC/DC regulator (TI TPS74401RGW, U17) @1.2V (MGTAVTT_FPGA)
- 4A PowerSoC DC-DC converter (Altera EN6347QI, U15) @3.3V (3V3FMC)
- 4A PowerSoC DC-DC converter (Altera EN6347QI, U7) @1.8V (FMC_VADJ)
Key Features
- Xilinx Virtex-7 FPGA module XC7VX330T-2FFG1157C (commercial temperature range)
- FPGA board designed as PCIe card is fitting in PCI Express x8 slots (PCIe 2.0 or higher)
- FMC High Pin Count (HPC) Connector
- 8 MGT-lanes available on PCIe interface
- DDR3 SO-DIMM Socket
- 256-Mbit (32-MByte) Quad SPI Flash memory (for configuration and operation) accessible through:
- FPGA
- JTAG port (SPI indirect (Bus width x4))
- External Clock Input via SMA coaxial connector
- 28 GTH transceivers, each with up to 13.1 Gbit/s data transmission rate
- FPGA configuration through:
- JTAG-connector
- SPI Flash memory
- Programmable quad PLL clock generator
- TI LMK04828B ultra low-noise high-performance clock synthesizer (jitter cleaner)
- On-board high-efficiency DC-DC converters
- Up to 202 FPGA I/O pins available on FMC connector (up to 101 LVDS-pairs possible)
- System management and power sequencing
- AES bit-stream encryption
- eFUSE bit-stream encryption
Additional assembly options are available for cost or performance optimization upon request.
Initial Delivery State
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Content
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Notes
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SPI Flash OTP Area
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Empty, not programmed
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Except serial number programmed by flash vendor.
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SPI Flash Quad Enable bit
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Programmed
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SPI Flash main array
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Demo design
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eFUSE USER
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Not programmed
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eFUSE Security
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Not programmed
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Table 1: Initial delivery state
Signals, Interfaces and Pins
FMC Connector
The FMC (FPGA Mezzanine Card) connector (J2) with high pin count (HPC) provides as an ANSI/VITA 57.1 standard a modular interface to the FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.
The connector supports single ended (with severeal VCCIO voltages available) and differential signaling as the I/O's are usable as LVDS-pairs.
The I/O signals are routed from the FPGA banks as LVDS-pairs to the connector:
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bank voltage VIO_B_FMC must be supplied by FMC connector pins J2-J39, J2-K40
bank's VREF-pin (VREF_B_M2C) available on FMC connector pin J2-K1 (extern reference voltage)
...
Table 2: FMC connector pin-outs of available logic banks of the FPGA.
The FMC connector provides also access to the MGT-banks of the FPGA. There are 10 high-speed data links (Xilinx GTH transceiver) available composed as differantial signaling pairs for both directions (RX/TX), means from card to (mezzanine) module and vice versa.
The MGT-banks have also clock input-pins which are exposed to the FMC connector. Following MGT-lanes are availabe on the FMC connector:
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1 reference clock from clock synthesizer U9 to bank's pins F6/F5
1 reference clock from programmable quad PLL clock generator U13 to bank's pins H6/H5
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Table 3: FMC connector pin-outs of available MGT-lanes of the FPGA
The FMC connector provides further interfaces like 'JTAG' and 'I²C' to the System Controller CPLD:
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FMC_TRST, pin D34
FMC_TCK, pin D29
FMC_TMS, pin D33
FMC_TDI, pin D30
FMC_TDO, pin D31
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FMC_SCL, pin C30
FMC_SDA, pin C31
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VCCIO: 3V3PCI
I²C-lines 3V3PCI pulled-up
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FMC_PRSNT_M2C_L, pin H2
FMC_PG_C2M, pin D1 (3V3FMC pull-up)
FMC_PG_M2C, pin F1 (3V3FMC pull-up)
...
'PG' = 'Power Good'-signal
'C2M' = carrier to (mezzanine) module
'M2C' = (mezzanine) module to carrier
internal System Controller CPLD signal assignment:
'FEX_0_N' <= 'FMC_PG_M2C'
'FMC_PG_C2M' <= 'FMC_PRSNT_M2C_L'
Table 4: FMC connector pin-outs of available interfaces to the System Controller CPLD
The FMC connector provides pins for reference clock input to the FPGA banks:
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Table 5: FMC connector pin-outs for reference clock input
Several VCCIO voltages are available on the FMC connector to operate the I/O's in order of the intended purpose:
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Table 6: Available VCCIO voltages on FMC connector
PCI Express Interface
The TEC0330 FPGA board is also a PCI Express card designed to fit in computing systems with PCI Express x8 slots (PCIe 2.0 or higher) and is PCIe Gen. 2 capable.
8 MGT-lanes are routed to the PCIe interface composed of RX/TX LVDS-pairs for each lane:
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1 reference clock from programmable quad PLL clock generator U13 to bank's pins AB6/AB5
1 reference clock from PCIe interface J1 to bank's pins AD6/AD5
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Table 7: MGT-lanes available on PCIe interface
JTAG Interfaces
JTAG interfaces are accessible on the TEC0330 board to program the FPGA-module or the System Controller CPLD:
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CPLD JTAG
VCCIO: 3V3PCI
Connector: J8
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J8-4
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FPGA JTAG
VCCIO: 1V8
Connector: J9
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FMC JTAG
VCCIO: 3.3VPCI
Connector: J2
...
Table 8: JTAG Interface on TEC0330 board
SO-DIMM Socket for DDR3-RAM
The TEC0330 board can be upgraded with a DDR3 SO-DIMM (204-pin). For this purpose the board is equipped with a 204-pin SO-DIMM socket U2. The DDR3 memory interface is routed to the FPGA banks 34, 35 and 36.
The reference clock signal for the DDR3 interface is generated by the quad programmable reference clock U13 and is applied to bank 35.
There is also a I²C-interface between the System Controller CPLD and the DDR3 memory interface:
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Table 9: I²C-interface between SC CPLD and DDR3 memory
System Controller CPLD
The System Controller CPLD is the central system management unit that provides numerous interfaces between the on-board peripherals and to the FPGA-module. The signals routed to the CPLD will be linked by the logic implemented in the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. So some interfaces between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence, the proper programing of the FPGA-module and to display its programming state.
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Table 10: VCCIO voltages of CPLD banks
Following table describes the interfaces and functionalities established by the CPLD, which weren't discussed elsewhere in this TRM:
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FPGA_IIC_SDA, pin 24
FPGA_IIC_SCL, pin 25
FPGA_IIC_OE, pin 19
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FPGA bank 16, pin V29
FPGA bank 16, pin W29
FPGA bank 16, pin W26
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VCCIO: 1V8
all lines 1V8 pulled-up
Following I²C-interfaces of are linked to the I²C-lines of 'FPGA_IIC' for data-transmission between the FPGA-module and on-board peripherals:
- FMC connector J2
- PCIe connector J1
- DC/DC converter U3 and U4 (LT LTM4676)
- Quad programmable PLL clock generator U13
Note: 'FPGA_IIC_OE' must kept high for I²C-operation.
For I²C-addresses refer to the data sheets of the components.
...
user I/O's
external LVDS-pairs
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10 I/O's
5 x differential signaling pairs
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EX0_P ... EX4_P
EX0_N ... EX4_N
...
pins can also be used for single-ended signaling
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user I/O's
internal LVDS-pairs
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13 I/O's
6 x differential signaling pairs
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FEX0_P ... FEX5_P
FEX0_N ... FEX5_N
FEX_DIR (single-ended I/O)
...
VCCIO: 1V8
pins can also be used for single-ended signaling
FPGA bank 18 has also reference clock input from FMC connector (CLK2, CLK3) and from clock synthesizer U9 (FCLK)
internal signal assignment:
'FEX_DIR' <= 'FMC_PRSNT_M2C_L'
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DONE, pin 7
PROGRAM_B, pin 8
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FPGA bank 0, pin V8
FPGA bank 0, pin U8
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PLL_SCL, pin 14
PLL_SDA, pin 15
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U13, pin 12
U13, pin 19
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VCCIO: 1V8
only 'PLL_SDA' 1V8 pulled-up
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F1SENSE, pin 99
F1PWM, pin 98
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J4-3 (low-active signal)
J4-4
...
internal signal assignment:
'FEX_5_P' <= 'F1SENSE'
'FEX_5_N' => 'F1PWM'
...
fast blinking, if FPGA not programmed
internal signal assignment:
'LED1' <= 'Button S2' or 'FEX0_P'
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PCIe control line RESET_B
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internal signal assignment:
'FEX_4_N' <= 'PCIE_RSTB'
...
Control Interface to clock synthesizer U9 (TI LMK04828B)
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SPI (3 I/O's),
4 I/O's
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CLK_SYNTH_SDIO, pin 75
CLK_SYNTH_SCK, pin 74
CLK_SYNTH_RESET, pin 54
CLK_SYNTH_CS, pin 53
CLK_SYNTH_SYNC, pin 52
LMK_STAT0, pin 62
LMK_STAT1, pin 63
...
U9, pin 20
U9, pin 19
U9, pin 5
U9, pin 18
U9, pin 6
U9, pin 31
U9, pin 48
...
'CLK_SYNTH_SDIO' 3V3PCI pulled-up
internal signal assignment:
'LMK_SCK' <= 'FEX_1_P'
'LMK_SDIO' <= 'FEX_1_N'
'LMK_CS' <= 'FEX_3_P'
'LMK_SYNC' <= 'FEX_3_N'
LMK_RESET <= 'FEX_4_P'
'FEX_2_P' => 'LMK_SDIO' (FEX_2_N must be 0)
'LMK_STAT0' and 'LMK_STAT1' signals will not be evaluated.
...
I²C (2 I/O's),
2 I/O's
...
LTM_SCL, pin 67
LTM_SDA, pin 66
LTM1_ALERT, pin 65
LTM2_ALERT, pin 64
...
U4, pin E6 and U3, pin E6
U4, pin D6 and U3, pin D6
U4, pin E5
U3, pin E5
...
all lines 3V3 pulled-up
LTM I²C-interface also accessible trough header J10
LTM1- and LTM2-Alert signals will not be evaluated.
...
EN_1V8, pin 58
PG_1V8, pin 59
EN_FMC_VADJ, pin 60
PG_FMC_VADJ, pin 61
EN_3V3, pin 51
PG_3V3, pin 57
...
U20, pin 27
U20, pin 28
U7, pin 27
U7, pin 28
U15, pin 27
U15, pin 28
...
The effective sequencing of the supply voltages depends on the currently programmed CPLD firmware.
EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously at start-up.
PG-signals will not be evaluated.
Table 11: System Controller CPLD functionalities
Clocking
The TEC0330 FPGA board has a sophisticated clock generation and conditioning system to meet the requirements of the Xilinx Virtex-7 GTH units with data transmission rates up to 13.1 Gb/s.
Clock sources
The board has the following sources to be provided with extern reference clock signals and on-board clock oscillators:
...
CLK_SYNTH_CLKIN0_P,
CLK_SYNTH_CLKIN0_N (GND)
...
CLK0_P, CLK0_N
...
GBTCLK0_M2C_P,
GBTCLK0_M2C_N
...
GBTCLK1_M2C_P,
GBTCLK1_M2C_N
...
PCIE_CLK_P,
PCIE_CLK_N
...
100 MHz
(PCIe spec.)
...
Table 12: Clock generator sources overview
Programmable PLL Clock (Phase-Locked Loop)
There is a Silicon Labs I²C programmable quad PLL clock generator Si5338A (U13) on-board. It's output frequencies can be programmed by using the I²C-bus with address 0x70.
A 25 MHz (U14) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.
Once running, the frequency and other parameters can be changed by programming the device using the I²C-bus connected between the FPGA (master) and clock generator (slave). Logic needs to be generated inside the FPGA-module to utilize I²C-bus correctly.
...
IN1/IN2
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CLKIN_5338_C_P, CLKIN_5338_C_N
...
reference clock signal from clock synthesizer U9
(100 nF decoupling capacitors and 100Ω termination resistor)
...
IN3
...
clock signal from reference clock oscillator SiTime SiT8208AI (U14).
...
IN4/IN6
...
IN5
...
not connected
...
CLK0 A/B
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DDR3_CLK_P, DDR3_CLK_N
...
CLK1 A/B
...
MGTCLK_5338_C_P,
MGTCLK_5338_C_N
...
reference clock signal to FPGA bank 115 MGT
(100 nF decoupling capacitors and 100Ω termination resistor)
...
CLK2 A/B
...
input clock signal to clock synthesizer U9
(100 nF decoupling capacitors)
...
MGTCLK2_5338_C_P,
MGTCLK2_5338_C_N
...
reference clock signal to FPGA bank 118 MGT
(100 nF decoupling capacitors and 100Ω termination resistor)
Table 13: Pin description of PLL clock generator Si5338A
Ultra low-noise high-performance clock synthesizer
The TEC0330 board utilizes an ultra low jitter clock synthesizer TI LMK04828B (U9) for conditioning and generating clean clock signals which are necessary for the GTH units of the Xilinx Virtex-7 FPGA-module.
The clock synthesizer can be controlled and programmed by its SPI-interface (SPI-slave) and other control lines, which are routed to the FPGA-module (SPI-master) and by-passed trough the System Controller CPLD. See section 'System Controller CPLD' for more detailed information.
Logic needs to be generated inside the FPGA-module to utilize SPI-bus correctly.
...
SPI-interface and control lines
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CLK_SYNTH_CLKIN0_P,
CLK_SYNTH_CLKIN0_N
...
input reference clock signal via SMA coaxial connector J3, connected to CLKin0* via serial decoupling capacitator 100nF.
CLKin0 to connected to GND via serial decoupling capacitator 100nF.
...
CLK_SYNTH_CLKIN1_P,
CLK_SYNTH_CLKIN1_N
...
CLK_SYNTH_DCLKOUT0_P,
CLK_SYNTH_DCLKOUT0_N
...
CLK_SYNTH_SDCLKOUT1_P,
CLK_SYNTH_SDCLKOUT1_N
...
CLKIN_5338_P,
CLKIN_5338_N
...
reference clock signal to quad PLL clock generator Si5338A (U13)
(100 nF decoupling capacitors and 100Ω termination resistor)
...
CLK_SYNTH_DCLKOUT4_P,
CLK_SYNTH_DCLKOUT4_N
...
CLK_SYNTH_SDCLKOUT7_P,
CLK_SYNTH_SDCLKOUT7_N
...
CLK_SYNTH_CLKIN2_P,
CLK_SYNTH_CLKIN2_N
...
reference clock signal to FPGA bank 18, pins J30/J31
(100 nF decoupling capacitors)
Table 14: Pin description of clock synthesizer TI LMK04828B
32 MByte Quad SPI Flash Memory
An 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron N25Q256A, U12) is provided for FPGA configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency. The memory can be accessed indirectly by the FPGA JTAG-port (J9) by implementing the functional logic for this purpose inside the FPGA.
Power and Power-On Sequence
Power Supply
The TEC0330 FPGA board is mainly suppled by the 6-pin 12V power connector J5, a minimum current capability of 3A for system startup is recommended. The FPGA board can't be used as a stand-alone board, it works only in use of a plugged PCI Express card (2.0 or higher).
Power Consumption
...
Table 15: Maximum current of power supplies. *to be determined
Power-On Sequence
The on-board voltages of the TEC0330 FPGA board will be powered-up in order of a determined sequence after the external voltages '12V' on connector J5 and '3V3PCI' on connector J1 are available.
Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.
Following diagram clarifies the sequence of enabling the particular on-board voltages:
Figure 3: FPGA board TEC0330-03 Power-On sequence diagram
Bank Voltages
...
114
115
116
117
118
...
MGTAVCC_FPGA
MGTVCCAUX_FPGA
MGTAVTT_FPGA
...
1.0V
1.8V
1.2V
...
MGT bank supply voltage
MGT bank auxiallary supply voltage
MGT bank termination circuits voltage
...
Table 16: Range of FPGAs bank voltages
See Xilinx Virtex-7 datasheet (DS183) for the voltage ranges allowed.
Power Rails
...
Table 17: Power rails of FPGA board on accessible connectors
Technical Specifications
Absolute Maximum Ratings
...
12V power supply voltage
...
-0.3
...
MachX02 Family Data Sheet
...
-55
...
+125
...
Table 18: Absolute maximum ratings
Recommended Operating Conditions
...
Table 19: Recommended operation conditions
| Note |
|---|
| Check Xilinx datasheet (DS183) for complete list of absolute maximum and recommended operating ratings. |
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Physical Dimensions
- board size: 106,65mm × 167,65mm
- Mating height with standard FMC connectors: 8.5 - 10 mm
- PCB thickness: 1.65 mm
Figure 4: Physical dimensions of the TEC0330-03 board. All dimensions are shown in millimeters.
Weight
156 g - Plain board.
Revision History
Hardware Revision History
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Hardware revision number is written on the PCB board together with the model number separated by the dash.
Document Change History
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Disclaimer
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