Page History
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- Xilinx Zynq Z-7030/Z-7035/Z-7045
- 1 GByte 32-Bit DDR3/L
- 32 MByte SPI Flash
- B2B Connectors 3 x 160 pins
- 250 I/O's, all HR and HP I/O
- 1 Gbit Ethernet PHY
- USB 2.0 OTG PHY
- 8 x GTX (7030: 4 GT)
- 2 GT Reference Clock inputs (7030: 1 REFCLK
- Reference clock input for PLL (optional)
- 2 x PLL outputs
- I2C
- 6 MIO
- RTC
- MAC Address EEPROM
I2C Address Map
| Device | ||
|---|---|---|
| RTC | 0x6F | |
| RTC RAM | 0x57 | |
| MAC Address EEPROM | 0x53 | |
| Si5338 PLL | 0x70 |
B2B connectors
| Include Page | ||||
|---|---|---|---|---|
|
...
Hardware Revision History
| Date | Revision | Notes | Link to PCN | Documentation Link |
|---|---|---|---|---|
| 2016-10-11 | 02 | Production release | TE0745-02 | |
| 2016-04-18 | 01 | Prototypes | TE0745-01 |
Hardware revision number is written on the PCB board together with the module model number separated by the dash.
Document Change History
| Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-02-05 | Jan Kumann | Initial document. |
Disclaimer
| Include Page | ||||
|---|---|---|---|---|
|
Overview
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