Page History
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- Xilinx ZYNQ-7000 family SoC, U1
- 256 Mbit Quad SPI Flash Memory Micron N25Q256A, U12
- Low Power Programmable Oscillator SiTime SiT8008BI @33.333 MHz, U12
- Low Power Programmable Oscillator SiTime SiT8008BI @25.000 MHz, U9
- Marvell Alaska 88E1512 Gigabit Ethernet PHY, U3
- Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16 Bit Word-Width), U3
- TI TPS51206 DDR3 Memory Termination Regulator with buffered reference votlage VTTREF, U18
- Intersil ISL12020MIRZ Real-Time-Clock, U24
- TI TCA9517 Level-shifting I²C bus repeater, U17
- LED D2 red
- LED D1 green
- Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16 Bit Word-Width), U5
- Altera Enpirion EN63A0QI 12A DCDC PowerSoC @1.0V (VCCINT), U4
- TI TPS74401RGW LDO DC/DC regulator @1.2V (MGTAVTT), U8
- TI TPS72018DRVR LDO DC/DC regulator @1.8V (MGTAUX), U6
- TI TPS74401RGW LDO DC/DC regulator @1.0V (MGTAVCC), U11
- Silicon Labs Si5338A I²C Programmable Quad Clock Generator, U13
- Low Power Programmable Oscillator SiTime SiT8008BI @25.000 MHz, U21
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J3
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J1
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J2
- 256 Mbit Quad SPI Flash Memory (Micron N25Q256A, U14
- Microchip USB3320 USB Transceiver PHY Transceiver, U32
- Low Power Programmable Oscillator SiTime SiT8008BI @52.000 MHz, U33
- Microchip 24AA025E48 EEPROM for MAC Address
- Lattice Semiconductor MachXO2-256HC System Controller CPLD, U2
Key Features
Industrial-grade Xilinx Zynq-7000 (Z-7030
/, Z-7035
/, Z-7045
- 1 GByte 32-Bit DDR3/L
- 32 MByte SPI Flash
- B2B Connectors 3 x 160 pins
- 250 I/O's, all HR and HP I/O
- 1 Gbit Ethernet PHY
- USB 2.0 OTG PHY
- 8 x GTX (7030: 4 GT)
- 2 GT Reference Clock inputs (7030: 1 REFCLK
- Reference clock input for PLL (optional)
- 2 x PLL outputs
- I2C
- 6 MIO
- RTC MAC Address EEPROM
) SoM
- Rugged for shock and high vibration
- 10/100/1000 Mbps Ethernet transceiver PHY
- MAC address EEPROM
- 16-Bit wide 1GB DDR3 SDRAM
- 32 MByte QSPI flash memory
- Programmable clock generator
- Plug-on module with 3 × 160-pin high-speed hermaphroditic strips
- 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on B2B connectors
- 8 GTX (high-performance transceiver) lanes (Z-7030: 4 GTX lanes)
- GTX (high-performance transceiver) clock input
- USB 2.0 OTG high-speed PHY
- On-board high-efficiency DC-DC converters
- 4.0 A x 1.0 V power rail
- 1.5 A x 1.5 V power rail
- 1.5 A x 1.8 V power rail
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- User LED
- Evenly-spread supply pins for good signal integrity
Additional assembly options are available for cost or performance optimization upon request.
I2C Address Map
Device | ||
---|---|---|
RTC | 0x6F | |
RTC RAM | 0x57 | |
MAC Address EEPROM | 0x53 | |
Si5338 PLL | 0x70 |
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