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Table 6: Ethernet PHY interface connections
USB Interface
MAC Address EEPROM
A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.
USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 25 MHz oscillator (U15).USB PHY connection
| PHY Pin | ZYNQ Pin | B2B Name | Notes |
|---|---|---|---|
| ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY |
| REFCLK | - | - | 52MHz from on board oscillator ( |
| U33) |
| REFSEL[0..2] | - | - | Reference clock frequency select, all set to GND selects 52MHz |
| RESETB |
| MIO7 | - |
| low-active reset |
| line | ||
| CLKOUT | MIO36 | - |
| set to VDDIO (1.8V |
| ) to select reference clock operation mode |
| DP, DM | - | OTG_D_P, OTG_D_N, pin J2-149 / J2-151 | USB data lines |
| CPEN | - | VBUS_V_EN, pin J2-141 | External USB power switch active high enable signal |
| VBUS | - | USB_VBUS, pin J2-145 | Connect to USB VBUS via a series of resistors, see reference schematics |
| ID | - | OTG_ID, pin J2-143 | For an A-Device connect to ground, for a B-Device left floating |
Table 7: USB PHY interface connections
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
MAC Address EEPROM
A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
RTC - Real Time Clock
An temperature compensated Intersil ISL12020M is used for as Real Time Clock (U16U24). Battery voltage must be supplied to the module clock from the main boardbase board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I2C I²C bus at slave address of 0x6F. General purpose RAM is at I2C of the clock can be accessed at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.
LEDs
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
D1 | Green | DONE | Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured. This LED will not operate if the SC can not power on the 3.3V output rail that also powers the 3.3V circuitry on the module. |
D2 | Red | SC | System main status LED. |
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Boot Modes
By default the TE-0715 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.
| MODE Signal State | Boot Mode |
|---|---|
High or open | QSPI |
Low or ground | SD Card |
System Controller CPLD
Special purpose pins are connected to System Controller CPLD and have following default configuration:
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| Clock | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
PS CLK | 33.3333 MHz | U11 | PS_CLK | PS subsystem main clock. |
ETH PHY reference | 25 MHz | U9 | - | - |
USB PHY reference | 52 MHz | U15 | - | - |
PLL reference | 25 MHz | U18 | - | - |
GT REFCLK0 | - | B2B | U9/V9 | Externally supplied from baseboard. |
GT REFCLK1 | 125 MHz | U10 Si5338 | U5/V5 | Default clock is 125 MHz. |
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PLL - Phase-Locked Loop
There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70.
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| I/O | Default Frequency | Notes |
|---|---|---|
IN1/IN2 | Externally supplied | Needs decoupling on base board. |
IN3 | 25MHz | Fixed input clock. |
IN4 | - | - |
IN5/IN6 | 125MHz | Ethernet PHY output clock. |
CLK0 | - | Not used, disabled. |
CLK1 | - | Not used, disabled. |
CLK2 A/B | 125MHz | MGT reference clock 1. |
CLK3A | - | Bank 34 clock input, default disabled, User clock. |
CLK3B | - | Not used, disabled. |
Power and Power-On Sequence
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See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 module.
Power Rails
Voltages on B2B Connectors | B2B JM1 Pin | B2B JM2-Pin | Input/ Output | Note |
|---|---|---|---|---|
| VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage. |
| 3.3VIN | 13, 15 | - | Input | Supply voltage. |
| VCCIO13 | 9, 11 | - | Input | High range bank voltage. |
| VCCIO34 | - | 5 | Input | TE0715-xx-15: high range bank voltage. TE0715-xx-30: high performance bank voltage. |
| VCCIO35 | - | 7, 9 | Input | TE0715-xx-15: high range bank voltage. TE0715-xx-30: high performance bank voltage. |
| VBAT_IN | 79 | - | Input | RTC battery-buffer supply voltage. |
| 3.3V | - | 10, 12 | Output | Internal 3.3V voltage level. |
| 1.8V | 39 | - | Output | Internal 1.8V voltage level. |
| DDR_PWR | - | 19 | Output | Internal 1.5V or 1.35V voltage level, depends on revision. |
| VREF_JTAG | 91 | Output | JTAG reference voltage (3.3V). |
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Bank | Schematic Name | Voltage | TE0715-xx-15 15 | TE0715-xx-30 30 |
|---|---|---|---|---|
| 500 | VCCO_MIO0_500 | 3.3V | - | - |
| 501 | VCCO_MIO1_501 | 1.8V | - | - |
| 502 | VCCO_DDR_502 | 1.5V | - | - |
| 0 Config | VCCO_0 | 3.3V | - | - |
| 13 HR | VCCO_13 | User | HR: 1.2V to 3.3V | HR: 1.2V to 3.3V |
| 34 HR/HP | VCCO_34 | User | HR: 1.2V to 3.3V | HP: 1.2V to 1.8V |
| 35 HR/HP | VCCO_35 | User | HR: 1.2V to 3.3V | HP: 1.2V to 1.8V |
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