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A Microchip 24AA025E48 EEPROM (U19U23) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C I²C slave address 0x500x53.
USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 25 MHz oscillator (U15).
| PHY Pin | ZYNQ Pin | B2B Name | Notes |
|---|---|---|---|
| ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY |
| REFCLK | - | - | 52MHz from on board oscillator (U33) |
| REFSEL[0..2] | - | - |
| all pins set to GND selects |
| the external reference clock frequency @52MHz | |||
| RESETB | MIO7 | - | low-active reset line |
| CLKOUT | MIO36 | - | set to VDDIO (1.8V) to select reference clock operation mode |
| DP, DM | - | OTG_D_P, OTG_D_N, pin J2-149 / J2-151 | USB data lines |
| CPEN | - | VBUS_V_EN, pin J2-141 | External USB power switch active high enable signal |
| VBUS | - | USB_VBUS, pin J2-145 | Connect to USB VBUS via a series of resistors, see reference schematics |
| ID | - | OTG_ID, pin J2-143 | For an A-Device connect to ground, for a B-Device left floating |
Table 7: USB PHY interface connections
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An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM of the clock RTC can be accessed at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD on bank 3, pin 4.
LEDs
| LED | ColorConnected | toconnected with | Description and Notes | ||
|---|---|---|---|---|---|
D1 | Green | SC CPLD, bank 3, pin 5 | System main status LED. | ||
D2 | Red | Zynq-Chip (U1), bank 0 (config bank), 'DONE' (pin W9) | Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as | DONE | Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured. This LED will not operate if the SC CPLD can not power on up the 3PL supply voltage.3V output rail that also powers the 3.3V circuitry on the module. |
D2 | Red | SC | System main status LED. |
Boot Modes
By default the TE-0715 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.
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High or open
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QSPI
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Low or ground
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SD Card
System Controller CPLD
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Table 8: LEDs of the SoC module
Boot Modes
The Zynq-module TE0745 supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.
The current boot mode will be set by the MIO0 pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'.
Following table describes how to set the control lines to configure the desired boot mode:
| Boot Mode | MIO5 (BOOTMODE_1) | MIO4 (BOOTMODE) | MIO3 | Note |
|---|---|---|---|---|
JTAG | 0 | 0 | 0 | - |
| NOR | 0 | 0 | 1 | MIO3 pin is not connected to QSPI Flash Memory. |
| NAND | 0 | 1 | 0 | - |
| QSPI Flash Memory | 1 | 0 | 0 | standard mode in current configuration |
| SD-Card | 1 | 1 | 0 | SD-Card on base-board necessary. |
Table 9: Selectable boot modes
System Controller CPLD
The System Controller CPLD is the central system management unit that provides numerous interfaces between the on-board peripherals and to the FPGA-module. The signals routed to the CPLD will be linked by the logic implemented in the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. So some interfaces between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence, the proper programing of the FPGA-module and to display its programming state.
| CPLD bank | CPLD bank's VCCIO |
|---|---|
| 0 | 3V3PCI |
| 1 | 3V3PCI |
| 2 | 3V3PCI |
| 3 | 1V8 |
Table 10: VCCIO voltages of CPLD banks
Following table describes the interfaces and functionalities established by the CPLD, which weren't discussed elsewhere in this TRM:
| CPLD functionality | interface | designated CPLD pins | connected with | Note |
|---|---|---|---|---|
| FPGA I²C connection between on-board peripherals and FPGA-module | I²C | FPGA_IIC_SDA, pin 24 FPGA_IIC_SCL, pin 25 FPGA_IIC_OE, pin 19 | FPGA bank 16, pin V29 FPGA bank 16, pin W29 FPGA bank 16, pin W26 | VCCIO: 1V8 all lines 1V8 pulled-up Following I²C-interfaces of are linked to the I²C-lines of 'FPGA_IIC' for data-transmission between the FPGA-module and on-board peripherals:
Note: 'FPGA_IIC_OE' must kept high for I²C-operation. For I²C-addresses refer to the data sheets of the components. |
user I/O's external LVDS-pairs | 10 I/O's 5 x differential signaling pairs | EX0_P ... EX4_P EX0_N ... EX4_N | IDC header J7 | pins can also be used for single-ended signaling |
user I/O's internal LVDS-pairs | 13 I/O's 6 x differential signaling pairs | FEX0_P ... FEX5_P FEX0_N ... FEX5_N FEX_DIR (single-ended I/O) | FPGA bank 18 | VCCIO: 1V8 pins can also be used for single-ended signaling FPGA bank 18 has also reference clock input from FMC connector (CLK2, CLK3) and from clock synthesizer U9 (FCLK) internal signal assignment: 'FEX_DIR' <= 'FMC_PRSNT_M2C_L' |
| FPGA programing control and state | 2 I/O's | DONE, pin 7 PROGRAM_B, pin 8 | FPGA bank 0, pin V8 FPGA bank 0, pin U8 | VCCIO: 1V8 |
| I²C-interface to quad programmable PLL clock generator | I²C | PLL_SCL, pin 14 PLL_SDA, pin 15 | U13, pin 12 U13, pin 19 | VCCIO: 1V8 only 'PLL_SDA' 1V8 pulled-up |
| Fan PWM control J4 | 2 I/O's | F1SENSE, pin 99 F1PWM, pin 98 | J4-3 (low-active signal) J4-4 | internal signal assignment: 'FEX_5_P' <= 'F1SENSE' 'FEX_5_N' => 'F1PWM' |
| Button S2 | 1 I/O | BUTTON, pin 77 | switch S2 | functionality depends on CPLD-firmware, activating pin 'PROGRAM_B' (low-active) and 'LED1' at standard configuration |
| LED1 | 1 I/O | LED1, pin 76 | LED D1 (green) | fast blinking, if FPGA not programmed internal signal assignment: 'LED1' <= 'Button S2' or 'FEX0_P' |
PCIe control line RESET_B | 1 I/O | 'PCIE_RSTB', pin 37 | PCIe connector J1-A11 (33R serial resistor) | internal signal assignment: 'FEX_4_N' <= 'PCIE_RSTB' |
Control Interface to clock synthesizer U9 (TI LMK04828B) | SPI (3 I/O's), 4 I/O's | CLK_SYNTH_SDIO, pin 75 CLK_SYNTH_SCK, pin 74 CLK_SYNTH_RESET, pin 54 CLK_SYNTH_CS, pin 53 CLK_SYNTH_SYNC, pin 52 LMK_STAT0, pin 62 LMK_STAT1, pin 63 | U9, pin 20 U9, pin 19 U9, pin 5 U9, pin 18 U9, pin 6 U9, pin 31 U9, pin 48 | 'CLK_SYNTH_SDIO' 3V3PCI pulled-up internal signal assignment: 'LMK_SCK' <= 'FEX_1_P' 'LMK_SDIO' <= 'FEX_1_N' 'LMK_CS' <= 'FEX_3_P' 'LMK_SYNC' <= 'FEX_3_N' LMK_RESET <= 'FEX_4_P' 'FEX_2_P' => 'LMK_SDIO' (FEX_2_N must be 0) 'LMK_STAT0' and 'LMK_STAT1' signals will not be evaluated. |
| Control Interface to DC/DC converters U3 and U4 (both LT LTM4676) | I²C (2 I/O's), 2 I/O's | LTM_SCL, pin 67 LTM_SDA, pin 66 LTM1_ALERT, pin 65 LTM2_ALERT, pin 64 | U4, pin E6 and U3, pin E6 U4, pin D6 and U3, pin D6 U4, pin E5 U3, pin E5 | all lines 3V3 pulled-up LTM I²C-interface also accessible trough header J10 LTM1- and LTM2-Alert signals will not be evaluated. |
| power-on sequence and monitoring | 6 I/O's | EN_1V8, pin 58 PG_1V8, pin 59 EN_FMC_VADJ, pin 60 PG_FMC_VADJ, pin 61 EN_3V3, pin 51 PG_3V3, pin 57 | U20, pin 27 U20, pin 28 U7, pin 27 U7, pin 28 U15, pin 27 U15, pin 28 | The effective sequencing of the supply voltages depends on the currently programmed CPLD firmware. EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously at start-up. PG-signals will not be evaluated. |
Table 11: System Controller CPLD functionalities
Clocking
The TEC0330 FPGA board has a sophisticated clock generation and conditioning system to meet the requirements of the Xilinx Virtex-7 GTH units with data transmission rates up to 13.1 Gb/s.
Clock sources
Clocking
| Clock | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
PS CLK | 33.3333 MHz | U11 | PS_CLK | PS subsystem main clock. |
ETH PHY reference | 25 MHz | U9 | - | - |
USB PHY reference | 52 MHz | U15 | - | - |
PLL reference | 25 MHz | U18 | - | - |
GT REFCLK0 | - | B2B | U9/V9 | Externally supplied from baseboard. |
GT REFCLK1 | 125 MHz | U10 Si5338 | U5/V5 | Default clock is 125 MHz. |
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