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Following table describes how to set the control lines to configure the desired boot mode:

Boot ModeMIO5 (BOOTMODE_1)MIO4 (BOOTMODE)

MIO3

Note

JTAG

000-
NOR001MIO3 pin is not connected to QSPI Flash Memory.
NAND010-
QSPI Flash Memory100standard mode in current configuration
SD-Card110SD-Card on base-board necessary.

Table 9: Selectable boot modes

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Other tasks of the System Controller CPLD are the monitoring of the power-on sequence, the proper programing of the FPGA-module and to display its programming state.

CPLD bankCPLD bank's VCCIO
0
3V3PCI
3.3V
1
3V3PCI
1.8V
2
3V3PCI
1.8V
3
1V8
3.3V

Table 10: VCCIO voltages of CPLD banks

Following table describes the interfaces and functionalities established by the CPLD, which weren't discussed elsewhere in this TRM:

CPLD functionalityinterfacedesignated CPLD pinsconnected withNote
FPGA I²C connection between on-board peripherals and FPGA-moduleI²C

FPGA_IIC_SDA, pin 24

FPGA_IIC_SCL, pin 25

FPGA_IIC_OE, pin 19

FPGA bank 16, pin V29

FPGA bank 16, pin W29

FPGA bank 16, pin W26

VCCIO: 1V8

all lines 1V8 pulled-up

Following I²C-interfaces of are linked to the I²C-lines of 'FPGA_IIC' for data-transmission between the FPGA-module and on-board peripherals:

  • FMC connector J2
  • PCIe connector J1
  • DC/DC converter U3 and U4 (LT LTM4676)
  • Quad programmable PLL clock generator U13

Note: 'FPGA_IIC_OE' must kept high for I²C-operation.

For I²C-addresses refer to the data sheets of the components.

user I/O's

external LVDS-pairs

10 I/O's

5 x differential signaling pairs

EX0_P ... EX4_P

EX0_N ... EX4_N

IDC header J7

pins can also be used for single-ended signaling

user I/O's

internal LVDS-pairs

13 I/O's

6 x differential signaling pairs

FEX0_P ... FEX5_P

FEX0_N ... FEX5_N

FEX_DIR (single-ended I/O)

FPGA bank 18

VCCIO: 1V8

pins can also be used for single-ended signaling

FPGA bank 18 has also reference clock input from FMC connector (CLK2, CLK3) and from clock synthesizer U9 (FCLK)

internal signal assignment:

'FEX_DIR' <= 'FMC_PRSNT_M2C_L'

FPGA programing control and state2 I/O's

DONE, pin 7

PROGRAM_B, pin 8

FPGA bank 0, pin V8

FPGA bank 0, pin U8

VCCIO: 1V8I²C-interface to quad programmable PLL clock generatorI²C

PLL_SCL, pin 14

PLL_SDA, pin 15

U13, pin 12

U13, pin 19

VCCIO: 1V8

only 'PLL_SDA' 1V8 pulled-up

Fan PWM control J42 I/O's

F1SENSE, pin 99

F1PWM, pin 98

J4-3 (low-active signal)

J4-4

internal signal assignment:

'FEX_5_P' <= 'F1SENSE'

'FEX_5_N' => 'F1PWM'

Button S21 I/OBUTTON, pin 77switch S2functionality depends on CPLD-firmware, activating pin 'PROGRAM_B' (low-active) and 'LED1' at standard configurationLED11 I/OLED1, pin 76LED D1 (green)

fast blinking, if FPGA not programmed

internal signal assignment:

'LED1' <= 'Button S2' or 'FEX0_P'

PCIe control line RESET_B

1 I/O'PCIE_RSTB', pin 37PCIe connector J1-A11 (33R serial resistor)

internal signal assignment:

'FEX_4_N' <= 'PCIE_RSTB'

Control Interface to clock synthesizer U9 (TI LMK04828B)

SPI (3 I/O's),

4 I/O's

CLK_SYNTH_SDIO, pin 75

CLK_SYNTH_SCK, pin 74

CLK_SYNTH_RESET, pin 54

CLK_SYNTH_CS, pin 53

CLK_SYNTH_SYNC, pin 52

LMK_STAT0, pin 62

LMK_STAT1, pin 63

U9, pin 20

U9, pin 19

U9, pin 5

U9, pin 18

U9, pin 6

U9, pin 31

U9, pin 48

'CLK_SYNTH_SDIO' 3V3PCI pulled-up

internal signal assignment:

'LMK_SCK' <= 'FEX_1_P'

'LMK_SDIO' <= 'FEX_1_N'

'LMK_CS' <= 'FEX_3_P'

'LMK_SYNC' <= 'FEX_3_N'

LMK_RESET <= 'FEX_4_P'

'FEX_2_P' => 'LMK_SDIO' (FEX_2_N must be 0)

'LMK_STAT0' and 'LMK_STAT1' signals will not be evaluated.

Control Interface to DC/DC converters U3 and U4 (both LT LTM4676)

I²C (2 I/O's),

2 I/O's

LTM_SCL, pin 67

LTM_SDA, pin 66

LTM1_ALERT, pin 65

LTM2_ALERT, pin 64

U4, pin E6 and U3, pin E6

U4, pin D6 and U3, pin D6

U4, pin E5

U3, pin E5

all lines 3V3 pulled-up

LTM I²C-interface also accessible trough header J10

LTM1- and LTM2-Alert signals will not be evaluated.

power-on sequence and monitoring6 I/O's

EN_1V8, pin 58

PG_1V8, pin 59

EN_FMC_VADJ, pin 60

PG_FMC_VADJ, pin 61

EN_3V3, pin 51

PG_3V3, pin 57

U20, pin 27

U20, pin 28

U7, pin 27

U7, pin 28

U15, pin 27

U15, pin 28

The effective sequencing of the supply voltages depends on the currently programmed CPLD firmware.

EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously at start-up.

     
     
     
     
     
     
     
     
     
     
     
     
PG-signals will not be evaluated.

Table 11: System Controller CPLD functionalities

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The TEC0330 FPGA board has a sophisticated clock generation and conditioning system to meet the requirements of the Xilinx Virtex-7 GTH units with data transmission rates up to 13.1 Gb/s.

Clock sources

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ClockFrequencyICFPGANotes

PS CLK

33.3333 MHz

U11

PS_CLK

PS subsystem main clock.

ETH PHY reference

25 MHz

U9

-

-

USB PHY reference

52 MHz

U15

-

-

PLL reference

25 MHz

U18

-

-

GT REFCLK0

-

B2B

U9/V9

Externally supplied from baseboard.

GT REFCLK1

125 MHz

U10 Si5338

U5/V5

Default clock is 125 MHz.

PLL - Phase-Locked Loop

There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70.

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