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| Boot Mode | MIO5 (BOOTMODE_1) | MIO4 (BOOTMODE) | MIO3 | Note |
|---|---|---|---|---|
JTAG | 0 | 0 | 0 | - |
| NOR | 0 | 0 | 1 | MIO3 pin is not connected to QSPI Flash Memory. |
| NAND | 0 | 1 | 0 | - |
| QSPI Flash Memory | 1 | 0 | 0 | standard mode in current configuration |
| SD-Card | 1 | 1 | 0 | SD-Card on base - board necessary. |
Table 9: Selectable boot modes
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The System Controller CPLD is the central system management unit that provides numerous interfaces between the on -board peripherals and to the FPGA-module. The signals routed to the CPLD will be linked by the logic implemented in the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. So some interfaces the SoC module which generates control signals and evaluates signals like the "Power Good" signals. Interfaces between the on-board peripherals and to the FPGASoC-module are by-passed, forwarded and controlled by the System Controller CPLD.Other tasks of the System Controller CPLD are the monitoring of the power-on sequence, the proper programing of the FPGA-module and to display its programming state.
| CPLD bank | CPLD bank's VCCIO |
|---|---|
| 0 | 3.3V |
| 1 | 1.8V |
| 2 | 1.8V |
| 3 | 3.3V |
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Following table describes the interfaces and functionalities established by the CPLD, which weren't discussed elsewhere in this TRMSystem Controller CPLD:
| CPLD functionality | interface | designated CPLD pins | connected with | Note |
|---|---|---|---|---|
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Overview
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