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Industrial-grade Xilinx Zynq-7000 (Z-7030, Z-7035, Z-7045) SoM
- Rugged for shock and high vibration
- 10/100/1000 Mbps Ethernet transceiver PHY
- EEPROM for storing Ethernet MAC Address
- 16-Bit wide 1GB DDR3 SDRAM
- 32 MByte QSPI flash memory
- Programmable clock generator
- Plug-on module with 3 × 160-pin high-speed hermaphroditic strips
- 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on B2B connectors
- 8 GTX (high-performance transceiver) lanes (Z-7030: 4 GTX lanes)
- USB 2.0 OTG high-speed PHY
- On-board high-efficiency DC-DC converters
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- User LED
- Evenly-spread supply pins for good signal integrity
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The System Controller CPLD is the central system management unit on the SoC module which generates control signals and evaluates and handles signals like the "Power Good"-signals of the on-board DC-DC converters. Interfaces between the on-board peripherals and the SoC-module are by-passed, forwarded and controlled by the System Controller CPLD.
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The SoC module has the following sources to be provided with extern reference clock signals and on-board clock oscillators:
| Clock source | Schematic name | Frequency | Clock input destination | Note |
|---|---|---|---|---|
| B2B connector J3, pin J3-74/J3-76 | CLKIN_N, CLKIN_P | user | Quad PLL clock Generator U16, pin 1/2 | - |
| B2B connector J3, pin J3-75/J3-77 | MGT_CLK0_P, MGT_CLK0_N | user | MGT-bank 112, pin R6/R5 | - |
| B2B connector J3, pin J3-81/J3-83 | MGT_CLK2_P, MGT_CLK2_N | user | MGT-bank 111, pin W6/W5 | - |
| SiTime SiT8008BI oscillator, U21 | - | 25.000 MHz | Quad PLL clock Generator U16, pin 3 | - |
SiTime SiT8008BI oscillator, U12 | PS_CLK | 33.333 MHz | Bank 500 (MIO0 bank), pin B24 | - |
| SiTime SiT8008BI oscillator, U23 | OTG-RCLK | 52.000 MHz | USB 2.0 Transceiver PHY U32, pin 26 | - |
| SiTime SiT8008BI oscillator, U9 | ETH_CLKIN | 25.000 MHz | Gbit Ethernet PHY U7, pin 34 | - |
Table 12: Clock sources overview
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Once running, the frequency and other parameters can be changed by programming the device using the I²C-bus connected between the Zynq-module (master) and reference clock signal generator (slave).
| Si5338A (U13) input | signal schematic name | Note |
|---|---|---|
IN1/IN2 | CLKIN_P, CLKIN_N | reference clock signal from B2B connector J3, pin J3-74/J3-76 (base board decoupling capacitors and termination resistor necessary) |
IN3 | reference clock signal from oscillator SiTime SiT8008BI (U21) | 25.000 MHz fixed frequency |
IN4/IN6 | pins put to GND | LSB (pin 'IN4') of the default I²C-adress 0x70 is zero |
IN5 | not connected | - |
| Si5338A (U13) output | signal schematic name | Note |
CLK0 A/B | MGTCLK1_P, MGTCLK1_N | reference clock signal to MGT-bank 112, pin U6/U5 (100 nF decoupling capacitors) |
CLK1 A/B | CLK1_P, CLK1_N | clock signal routed to B2B connector, pin J3-80/J3-82 |
CLK2 A/B | CLK2_P, CLK2_N | clock signal routed to B2B connector, pin J3-86/J3-88 |
| CLK3 A/B | MGTCLK3_P, MGTCLK3_N | reference clock signal to MGT-bank 111, pin AA6/AA5 (100 nF decoupling capacitors) |
Table 13: Pin description of PLL clock generator Si5338A
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| Power Input Pin | Max Current |
|---|---|
| PL_VIN | TBD* |
| PS_VIN | TBD* |
| PS_3.3VIN3V | TBD* |
* TBD - To Be Determined Table 14: Maximum current of power supplies. *to be determined soon with reference design setup.
Lowest power consumption is achieved when and highest efficiency of on board DC/DC regulators it is recommended to powering the module from one single 3.3V supply. When using split All input power supplies have a nominal value of 3.3V/5V supplies . Although the power consumption (and heat dissipation) will rise due to the DC-DC converter efficiency (it decreases when VIN/VOUT ratio rises). Typical module power consumption is between 2-3Winput power supplies can be powered up in any order, it is recommended to power them up simultaneously.
Power-On Sequence
For highest efficiency of on board DC/DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.
It is important that all baseboard I/Os are 3It is important that all baseboard I/Os are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 modulefor additional information. User should also check related base board documentation when intending base board design for TE0745 module.
The on-board voltages of the TEC0330 FPGA board will be powered-up in order of a determined sequence after the external voltages '12V' on connector J5 and '3V3PCI' on connector J1 are available.
Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.
Following diagram clarifies the sequence of enabling the particular on-board voltages:
Power-up sequence at start-up
The Trenz TE0782 SoM is equipped with two quad DC/DC-voltage-regulators to generate the required on-board voltages with the values 1V, 3.3V, 1.8V, 1.2V_MGT, 1V_MGT.
There are also additional voltage regulators on board to generate the voltages 1.5V, VTT, VTTREF and 1.8V_MGT.
On this SoM the sequence of powering up of the required on-board voltages is handled internally by the system controller CPLD processing the "POWER GOOD"-signals from the voltage-regulators.
To avoid any demages to the SoM, check for stabilized on-board voltages in steady state before powering up the SoC's I/O bank voltages VCCIO.
The "POWER GOOD"-signals can be checked on the system controller CPLD.
Pay attention to the voltage level of the I/O-signals, which must not be higher then VCCIO+0.4V.Power Rails
Voltages on B2B | B2B J1 Pin | B2B |
|---|
J2 Pin | B2B |
|---|
| J3 Pin | Input/ | Note |
|---|---|---|
| PL_VIN |
147, 149, 151, 153, | - | - | Input | supply voltage | |
| PS_VIN | - | 154, 156, 158 | - | Input | supply voltage |
| PS_3.3V | - | 160 | - | Input |
| supply voltage |
| VCCIO12 |
| 54, |
| 55 | - | - | Input |
| high range bank voltage |
| VCCIO13 | 112, 113 | - |
| - | Input |
| high range bank voltage |
| VCCIO33 |
| - |
| - | 115, 120 | Input | high performance bank voltage |
| VCCIO34 | 29, 30 | - |
| Input |
TE0715-xx-15: high range bank voltage.
TE0715-xx-30:| high performance bank voltage | |||||
| VCCIO35 | 87, 88 | - | Input | high performance bank voltage |
| VBAT_IN | 146 |
| - | - | Input | RTC battery-buffer supply voltage |
| PS_ |
| 1.8V |
| - |
| 130 | - |
| Output |
| internal 1. |
| 8V voltage level (Process System supply) |
Table 15: Power rails of the SoC module on accessible connectors
Bank Voltages
Bank
500 VCCO_MIO0_500 3.3V - - 501 VCCO_MIO1_501 1.8V - - 502 VCCO_DDR_502 1.5V - - 0 Config VCCO_0 3.3V - - 13 HR VCCO
3V
HR
3
3V
HR/
VCCO
HR: 1.2V to 3.3V
8V
HR/
VCCO
HR
3.3V
HP: 1.2V to 1.8V
Bank | Schematic Name | Voltage |
|---|
TE0715-xx-15
TE0715-xx-30
Voltage Range | |||
|---|---|---|---|
| 0 (config) | VCCIO_0 | PL_1.8V if R67 is equipped | - |
| 500 (MIO0) | PS_1.8V | 1.8V | - |
| 501 (MIO1) | PS_1.8V | 1.8V | - |
| 502 (DDR3) | 1.35V | 1.35V | - |
| 12 HR | VCCIO_12 | User | HR: 1.2V to 3.3V |
| 13 HR | VCCIO |
| _13 | User | HR: 1.2V to 3. |
| 3V | |||
| 33 HP | VCCIO_33 | User | HP |
| : 1.2V to |
| 1. |
| 8V |
| 34 |
| HP |
| VCCIO_34 | User |
| HP: 1.2V to 1. |
| 8V |
| 35 |
| HP |
| VCCIO_35 | User |
| HP: 1.2V to |
B2B connectors
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| 1.8V |
Table 16: Range of SoC module bank voltages
B2B connectors
| Include Page | ||||
|---|---|---|---|---|
|
Variants Currently In Production
| Module Variant | Zynq SoC | SoC Junction Temperature | Operating Temperature Range |
|---|---|---|---|
Technical Specification
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Absolute Maximum Ratings
Parameter | Min | Max | Units | Notes |
|---|---|---|---|---|
VIN supply voltage | -0.3 | 6.0 | V | - |
3.3VIN supply voltage | -0.4 | 3.6 | V | - |
| VBAT supply voltage | -1 | 6.0 | V | - |
| PL IO bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | V | - |
PL IO bank supply voltage for HP I/O banks (VCCO) | -0.5 | 2.0 | V | TE0715-xx-15 does not have HP banks. |
| I/O input voltage for HR I/O banks | -0.4 | VCCO_X+0.55 | V | - |
| I/O input voltage for HP I/O banks | -0.55 | VCCO_X+0.55 | V | TE0715-xx-15 does not have HP banks. |
| GT receiver (RXP/RXN) and transmitter (TXP/TXN) | -0.5 | 1.26 | V | - |
Voltage on module JTAG pins | -0.4 | VCCO_0+0.55 | V | VCCO_0 is 3.3V nominal. |
Storage temperature | -40 | +85 | °C | - |
| Storage temperature without the ISL12020MIRZ | -55 | +100 | °C | - |
| Note |
|---|
| Assembly variants for higher storage temperature range are available on request. |
| Note |
| Please check Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for complete list of absolute maximum and recommended operating ratings. |
Recommended Operating Conditions
| Parameter | Min | Max | Units | Notes | Reference Document |
|---|---|---|---|---|---|
| VIN supply voltage | 2.5 | 5.5 | V | ||
| 3.3VIN supply voltage | 3.135 | 3.465 | V | ||
| VBAT_IN supply voltage | 2.7 | 5.5 | V | ||
PL I/O bank supply voltage for HR I/O banks (VCCO) | 1.14 | 3.465 | V | Xilinx datasheet DS191 | |
PL I/O bank supply voltage for HP I/O banks (VCCO) | 1.14 | 1.89 | V | TE0715-xx-15 does not have HP banks | Xilinx datasheet DS191 |
| I/O input voltage for HR I/O banks | (*) | (*) | V | (*) Check datasheet | Xilinx datasheet DS191 or DS187 |
| I/O input voltage for HP I/O banks | (*) | (*) | V | TE0715-xx-15 does not have HP banks (*) Check datasheet | Xilinx datasheet DS191 |
| Voltage on Module JTAG pins | 3.135 | 3.465 | V | VCCO_0 is 3.3 V nominal |
| Note |
|---|
| Please check Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for complete list of absolute maximum and recommended operating ratings. |
Physical Dimensions
Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
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