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The B2B connector J1 and J2 provide also access to the MGT-banks of the SoC module. There are 8 high-speed data links (Xilinx GTX transceiver) available composed as differential signaling pairs for both directions (RX/TX), means from module to base-board and vice versa.
The MGT-banks have also clock input-pins which are exposed to the B2B connector J3. Following MGT-lanes are available on the B2B connectors:
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| Boot Mode | MIO5 (BOOTMODE_1) | MIO4 (BOOTMODE) | MIO3 | Note |
|---|---|---|---|---|
JTAG | 0 | 0 | 0 | - |
| NOR | 0 | 0 | 1 | MIO3 pin is not connected to QSPI Flash Memory |
| NAND | 0 | 1 | 0 | - |
| QSPI Flash Memory | 1 | 0 | 0 | standard mode in current configuration |
| SD-Card | 1 | 1 | 0 | SD-Card on base board necessary |
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