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Following table describes the interfaces and functionalities established by the System Controller CPLD:

Table 11: System Controller CPLD functionalities

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Variants Currently In Production

Module Variant	Zynq SoC	SoC Junction Temperature	Operating Temperature Range

Parameter	Min	Max	Units	Notes
PL_VIN	-0.3	5	V	TI TPS720 data sheet
PS_VIN	-0.3	7	V	TI TPS82085 data sheet
PS_3.3V	3.135	3.465	V	3.3V nominal ± 5%
VBAT supply voltage	-1	6.0	V	ISL12020MIRZ data sheet
PL IO bank supply voltage for HR I/O banks (VCCO)	-0.5	3.6	V	-
PL IO bank supply voltage for HP I/O banks (VCCO)	-0.5	2.0	V	-
I/O input voltage for HR I/O banks	-0.4	VCCO_X+0.55	V	-
I/O input voltage for HP I/O banks	-0.55	VCCO_X+0.55	V	-
GT receiver (RXP/RXN) and transmitter (TXP/TXN)	-0.5	1.26	V	-
Voltage on module JTAG pins	-0.3	3.6	V	MachX02 Family data sheet
Storage temperature	-40	+85	°C	ISL12020MIRZ data sheet
Storage temperature without the ISL12020MIRZ	-55	+100	°C	Intelligent memory datasheet

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Parameter	Min	Max	Units	Notes	Reference Document
PL_VIN	3.3	4.5	V	-	TI TPS720 data sheet
PS_VIN	3.3	6.0	V	-	TPS82085 TI TPS82085 data sheet
PS_3.3V	3.135	3.465	V	-	3.3V nominal ± 5%
VBAT_IN supply voltage	2.7	5.5	V	-	ISL12020MIRZ data sheet
PL I/O bank supply voltage for HR I/O banks (VCCO)	1.14	3.465	V	-	Xilinx datasheet DS191
PL I/O bank supply voltage for HP I/O banks (VCCO)	1.14	1.89	V	-	Xilinx datasheet DS191
I/O input voltage for HR I/O banks	-0.20	VCCO_X+0.20	V	-	Xilinx datasheet DS191
I/O input voltage for HP I/O banks	-0.20	VCCO_X+0.20	V	-	Xilinx datasheet DS191
GT receiver (RXP/RXN) and transmitter (TXP/TXN)	(*)	(*)	V	(*) Check datasheet	Xilinx datasheet DS191
Voltage on Module JTAG pins	3.135	3.6	V	JTAG-signals forwarded to Zynq-module config bank 0	MachX02 Family Data Sheet

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Date	Revision	Contributors	Description
2017-03-2831		Ali Naseri, Jan Kumann	first TRM release
2017-02-05	V1	Jan Kumann	Initial document.

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