Page History
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Clock | Default Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
| CLK125MHz | 25 MHz | U8 | T14 | Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V IO-Standard on FPGA bank. |
| MGT_CLK | 125MHz | U2 | B6/B5 | Frequency depends on the module variant |
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Date | Revision | Authors | Description |
|---|---|---|---|
| 2017-03-20 | John Hartfiel | Notes on Clocking section. | |
| 2017-01-27 | v.25 | Jan Kumann | New block diagram. |
| 2016-12-01 | V17v.17 | Jan Kumann | Changes in the document structure, few corrections. |
| 2016-11-18 | v.14V14 | Thorsten Trenz, Emmanuel Vassilakis | Hardware revision 02 specific changes. |
2016-06-01 | V9v.9 | Antti Lukats | Initial version. |
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