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The B2B connector J1 and J2 provide also access to the MGT-banks of the SoC module. There are 8 high-speed data links lanes (Xilinx GTX transceiver) available composed as differential signaling pairs for both directions (RX/TX).
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| Bank | I/O signal count | LVDS-pairs count | MGT-lanes count (RX/TX LVDS-pairs) | MGT bank's reference clock inputs (LVDS-pairs) | Notes |
|---|---|---|---|---|---|
| Bank 111 | 20 | 10 | 4 | 1 reference clock signal (MGT_CLK3) from programmable quad PLL clock generator U16 to bank's pins AA6/AA5. 1 reference clock signal (MGT_CLK2) from B2B connector J3 (pins J3-81/J3-83) to bank's pins W6/W5. | - |
| Bank 112 | 20 | 10 | 4 | 1 reference clock signal (MGT_CLK1) from programmable quad PLL clock generator U16 to bank's pins U6/U5. 1 reference clock signal (MGT_CLK0) from B2B connector J3 (pins J3-75/J3-77) to bank's pins R6/R5. | - |
Table 3: B2B connector pin-outs of available MGT-lanes of the SoC module
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| Interfaces | I/O signal count | pin schematic names / B2B pins | connected with | Notes | ||
|---|---|---|---|---|---|---|
| JTAG | 5 | TMS, pin J1-144 TDI, pin J1-142 TDO, pin J1-145 TCK, pin J1-143 JTAG_EN, pin J1-148 | SC CPLD, bank 0 |
At normal operation the JTAG-signals will be forwarded to the SoC module. Else the JTAG_EN pin must be high or open to update the CPLD firmware via JTAG-interface. VCCIO: PS_3.3V | ||
| I²C | 2 | I2C_33_SCL, pin J2-119 I2C_33_SDA, pin J2-121 | RTC, U24 SC CPLD, U2 MAC Address EEPROM, U23 Zynq-module, U1 Quad programmable PLL clock generator, U16 | The I²C-interface of the RTC U24 (pin 12: SCL, pin 11: SDA) and the B2B-connector J2 are operating with the reference voltage PS_3.3V. Following component's I²C-interfaces are operating with the reference voltage PS_1.8V (voltage level shifting 3.3V ↔ 1.8V via I²C bus repeater U17):
Component's I²C Addresses:
| ||
| control lines | 5 | RST_IN_N, pin J2-131 | SC CPLD bank 0, pins 25; Reset Circuit U41, pin 3 | Low-active Power-On reset pin, controls POR_B-signal (bank 500, pin C23) of Zynq-chip. | ||
| PS_SRST, pin J2-152 | SC CPLD bank 2, pin 12; Zynq-chip bank 501, pin A22 | Low-active system-reset pin of Zynq-chip. | ||||
| BOOTMODE, pin J2-133 | Zynq-chip bank 500, pin F24 | Control line which sets in conjunction with signal 'BOOTMODE1' the boot source of the Zynq-chip. See section "Boot Modes". | ||||
| PWR_PL_OK, pin J2-135 | SC CPLD bank 0, pin 27; PG-signal DCDC-converter U8, pin 9 | Indicates stable state of PL supply voltage (low-active) after power-up sequence. | ||||
| PWR_PS_OK, pin J2-139 | SC CPLD bank 0, pin 28; PG-signal DCDC-converter U31, pin 2 | Indicates stable state of PS supply voltage (low-active) after power-up sequence. |
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