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The I/O signals are routed from the SoC's PL banks as LVDS-pairs to the B2B connectors.

BankTypeB2B ConnectorI/O Signal CountLVDS Pairs CountVCCO Bank VoltageNotes
12HRJ15024
user (
VCCIO_12
)

pins J1-54, J1-55		supported voltages from 1.2V to 3.3V
13HRJ15024
user (
VCCIO_13
)

pins J1-112, J1-113		supported voltages from 1.2V to 3.3V
33HPJ35024VCCIO_33
pins J3-115, J3-120		supported voltages from 1.2V to 1.8V
34HPJ25024
user (
VCCIO_34
)

pins J2-29, J2-30		supported voltages from 1.2V to 1.8V
35HPJ25024
user (
VCCIO_35
)

pins J2-87, J2-88		supported voltages from 1.2V to 1.8V
500MIOJ25-1.8V-
501MIOJ312-1.8V-

Table 2:  B2B connector pin-outs of available PL and PS banks of the SoC module

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The MGT-banks have also clock input-pins which are exposed to the B2B connector J3. Following MGT-lanes are available on the B2B connectors:

BankTypeB2B ConnectorCount of MGT LanesSchematic Names / Connector PinsMGT Bank's Reference Clock Inputs (LVDS pairs)
Bank 111GTXJ14

MGT_RX4_P, MGT_RX4_N, pins J1-23, J1-21
MGT_TX4_P, MGT_TX4_N, pins J1-22, J1-20

MGT_RX5_P, MGT_RX5_N, pins J1-17, J1-15
MGT_TX5_P, MGT_TX5_N, pins J1-16, J1-14

MGT_RX6_P, MGT_RX6_N, pins J1-11, J1-9
MGT_TX6_P, MGT_TX6_N, pins J1-10, J1-8

MGT_RX7_P, MGT_RX7_N, pins J1-3, J1-5
MGT_TX7_P, MGT_TX7_N, pins J1-4, J1-6

1 reference clock signal (MGT_CLK3) from programmable
quad PLL clock generator U16 to bank's pins AA6/AA5.

1 reference clock signal (MGT_CLK2) from B2B connector
J3 (pins J3-81/J3-83) to bank's pins W6/W5.

Bank 112GTXJ34

MGT_RX3_P, MGT_RX3_N, pins J3-68, J3-70
MGT_TX3_P, MGT_TX3_N, pins J3-69, J3-71

MGT_RX2_P, MGT_RX2_N, pins J3-62, J3-64
MGT_TX2_P, MGT_TX2_N, pins J3-63, J3-65

MGT_RX1_P, MGT_RX1_N, pins J3-56, J3-58
MGT_TX1_P, MGT_TX1_N, pins J3-57, J3-59

MGT_RX0_P, MGT_RX0_N, pins J3-50, J3-52
MGT_TX0_P, MGT_TX0_N, pins J3-51, J3-53

1 reference clock signal (MGT_CLK1) from programmable
quad PLL clock generator U16 to bank's pins U6/U5.

1 reference clock signal (MGT_CLK0) from B2B connector
J3 (pins J3-75/J3-77) to bank's pins R6/R5.

Table 3: B2B connector pin-outs of available MGT lanes of the SoC module

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JTAG Interface

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JTAG access is provided through the SoC's PS configuration bank 0 and available on B2B connector J1.

JTAG SignalB2B Connector Pin
TCKJ1-143
TDIJ1-142
TDOJ1-145
TMSJ1-144

Table 4: B2B connector pin-out of JTAG interface

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System Controller I/O Pins

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Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Pin NameModeFunctionB2B Connector PinDefault Configuration
JTAG_ENInputJTAG SelectJ1-148
Note
JTAG_EN pin in B2B connector J1-148 should be kept low or grounded for normal operation!

At normal operation the JTAG-signals will be forwarded to the SoC module.
Else the JTAG_EN pin must be high or open to update the CPLD firmware via JTAG-interface.

VCCIO: PS_3.3V

 

RST_IN_NInputResetJ2-131Low-active Power-On reset pin, controls POR_B-signal (bank 500, pin C23) of Zynq-chip.
PS_SRSTInputResetJ2-152Low-active system-reset pin of Zynq-chip.
BOOTMODEInputBootmodeJ2-133Control line which sets in conjunction with signal 'BOOTMODE1' (B2B-pin J2-133)
the boot source of the Zynq-chip. See section "Boot Modes".
PWR_PL_OKOutputPower GoodJ2-135Indicates stable state of PL supply voltage (low-active) after power-up sequence.
PWR_PS_OKOutputPower GoodJ2-139Indicates stable state of PS supply voltage (low-active) after power-up sequence.





Interface on B2B connectors 

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