Page History
...
| Pin Name | Mode | Function | B2B Connector Pin | Default Configuration | ||
|---|---|---|---|---|---|---|
| JTAG_EN | Input | JTAG Select | J1-148 |
At normal operation the JTAG-signals will be forwarded to the SoC module. VCCIO: PS_3.3V | ||
| RST_IN_N | Input | Reset | J2-131 | Low-active Power-On reset pin, controls POR_B-signal (bank 500, pin C23) of Zynq-chip. | ||
| PS_SRST | Input | Reset | J2-152 | Low-active system-reset pin of Zynq-chip. | ||
| BOOTMODE | Input | Bootmode | J2-133 | Control line which sets in conjunction with signal 'BOOTMODE1' (B2B-pin J2-133) the boot source of the Zynq-chip. See section "Boot Modes". | ||
| PWR_PL_OK | Output | Power Good | J2-135 | Indicates stable state of PL supply voltage (low-active) after power-up sequence. | ||
| PWR_PS_OK | Output | Power Good | J2-139 | Indicates stable state of PS supply voltage (low-active) after power-up sequence. |
On-board LEDs
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
Clocking
| Clock | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
PS CLK | 33.3333 MHz |
| PS_CLK | PS subsystem main clock. |
Interface on B2B connectors
...
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
I2C Interface
On-board I2C devices are connected to MIO.. and MIO.. which are configured as I2C... by default. I2C addresses for on-board devices are listed in the table below:
| I2C Device | I2C Address | Notes |
|---|---|---|
RTC - Real Time Clock
An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD on bank 3, pin 4.
...
Table 8: LEDs of the SoC module
Boot
...
Process
The Zynq-module TE0745 supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.
...
Table 9: Selectable boot modes
...
On-board Peripherals
Processing System (PS) Peripherals
| Name | IC | ID | PS7 | MIO | Notes |
|---|---|---|---|---|---|
| SPI Flash | S25FL256SAGBHI20 | U14 | QSPI0 | MIO1..MIO6 |
The System Controller CPLD is the central system management unit on the SoC module which generates control signals and evaluates and handles signals like the "Power Good"-signals of the on-board DC-DC converters. Interfaces between the on-board peripherals and the SoC-module are by-passed, forwarded and controlled by the System Controller CPLD.
...
Table 11: System Controller CPLD functionalities
Clocking
Clock sources
The SoC module has the following sources to be provided with extern reference clock signals and on-board clock oscillators:
...
Overview
Content Tools