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| Pin Name | Mode | Function | B2B Connector Pin | Default Configuration | ||
|---|---|---|---|---|---|---|
| JTAG_EN | Input | JTAG Select | J1-148 |
At normal operation the JTAG-signals will be forwarded to the SoC module. VCCIO: PS_3.3V | ||
| RST_IN_N | Input | Reset | J2-131 | Low-active Power-On reset pin, controls POR_B-signal (bank 500, pin C23) of Zynq-chip. | ||
| PS_SRST | Input | Reset | J2-152 | Low-active PS system-reset pin of Zynq-chip. | ||
| BOOTMODE | Input | Bootmode | J2-133 | Control line which sets in conjunction with signal 'BOOTMODE1' (B2B-pin J2-133) Permanent high in standard SC-CPLD firmware. | ||
| PWR_PL_OK | Output | Power Good | J2-135 | Indicates stable state of PL supply voltage (low-active) after power-up sequence. | ||
| PWR_PS_OK | Output | Power Good | J2-139 | Indicates stable state of PS supply voltage (low-active) after power-up sequence. |
On-board LEDs
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Clocking
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PS CLK
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33.3333 MHz
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PS_CLK
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PS subsystem main clock.
Interface on B2B connectors
The B2B connector provides further interfaces like 'JTAG' and 'I²C' to the System Controller CPLD:
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I2C_33_SCL, pin J2-119
I2C_33_SDA, pin J2-121
RTC, U24
SC CPLD, U2
MAC Address EEPROM, U23
Zynq-module, U1
Quad programmable PLL clock generator, U16
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The I²C-interface of the RTC U24 (pin 12: SCL, pin 11: SDA) and the B2B-connector J2 are operating with the reference voltage PS_3.3V.
Following component's I²C-interfaces are operating with the reference voltage PS_1.8V (voltage level shifting 3.3V ↔ 1.8V via I²C bus repeater U17):
- SC CPLD U2, bank 2, pins 16 (SDA), 17 (SCL)
- MAC Address EEPROM U23, pins 1 (SCL), 3 (SDA)
- Zynq-chip U1, bank 500 (MIO0), pins A25 (SCL), B26 (SDA)
- Quad programmable PLL clock generator U16: pins 12 (SCL), 19 (SDA)
Component's I²C Addresses:
- RTC: 0x6F
- RTC RAM: 0x57
- MAC Address EEPROM: 0x53
- Quad programmable PLL clock generator: 0x70
| EN_PL | Output | Enable-signal | - | Low active Enable-signal for activating PL supply voltage. Permanent high in standard SC-CPLD firmware. |
| MIO8 | Input/Output | PS MIO | - | User I/O (pulled-up to PS_1.8V) |
| MIO0 | Input/Output | PS MIO | J2-137 | User I/O |
| RTC_INT | Input | Interrupt-signal | - | Interrupt-signal from on-board RTC |
On-board LEDs
| LED | Color | connected to | Description and Notes |
|---|---|---|---|
D1 | Green | SC CPLD, bank 3, pin 5 | System main status LED, blinking frequently or at system activity |
D2 | Red | Zynq-Chip (U1), bank 0 (config bank), 'DONE' (pin W9) | Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured. This LED will not operate if the SC CPLD can not power up the PL supply voltage. |
Table 8: LEDs of the SoC module
Clocking
The SoC module has the following sources to be provided with extern reference clock signals and on-board clock oscillators:
| Clock source | Schematic name | Frequency | Clock input destination | Note |
|---|---|---|---|---|
| B2B connector J3, pin J3-74/J3-76 | CLKIN_N, CLKIN_P | user | Quad PLL clock Generator U16, pin 1/2 | - |
| B2B connector J3, pin J3-75/J3-77 | MGT_CLK0_P, MGT_CLK0_N | user | MGT-bank 112, pin R6/R5 | - |
| B2B connector J3, pin J3-81/J3-83 | MGT_CLK2_P, MGT_CLK2_N | user | MGT-bank 111, pin W6/W5 | - |
| SiTime SiT8008BI oscillator, U21 | - | 25.000 MHz | Quad PLL clock Generator U16, pin 3 | - |
SiTime SiT8008BI oscillator, U12 | PS_CLK | 33.333 MHz | Bank 500 (MIO0 bank), pin B24 | - |
| SiTime SiT8008BI oscillator, U23 | OTG-RCLK | 52.000 MHz | USB 2.0 Transceiver PHY U32, pin 26 | - |
| SiTime SiT8008BI oscillator, U9 | ETH_CLKIN | 25.000 MHz | Gbit Ethernet PHY U7, pin 34 | - |
Table 12: Clock sources overview
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Table 4: B2B connector pin-outs of available interfaces
Default MIO Mapping
| MIO | Function | connected with | Notes | MIO | Function | connected with | Notes | |
|---|---|---|---|---|---|---|---|---|
| 0 | GPIO | J2-137, SC CPLD bank 2, pin 14 | user I/O on B2B | 16..27 | ETH0 | Ethernet PHY U7 | RGMII | |
| 1 | QSPI0 | QSPI Flash Memory U14, pin C2 | SPI Flash-CS | 28..39 | USB0 | USB PHY U32 | ULPI | |
| 2 | QSPI0 | QSPI Flash Memory U14, pin D3 | SPI Flash-DQ0 | 40 | GPIO | J2-150 | user I/O on B2B | |
| 3 | QSPI0 | QSPI Flash Memory U14, pin D2 | SPI Flash-DQ1 | 41 | GPIO | J2-152 | user I/O on B2B | |
| 4 | QSPI0 | QSPI Flash Memory U14, pin C4 | SPI Flash-DQ2 | 42 | GPIO | J2-154 | user I/O on B2B | |
| 5 | QSPI0 | QSPI Flash Memory U14, pin D4 | SPI Flash-DQ3 | 43 | GPIO | J2-156 | user I/O on B2B | |
| 6 | QSPI0 | QSPI Flash Memory U14, pin B2 | SPI Flash-SCK | 44 | GPIO | J2-158 | user I/O on B2B | |
| 7 | GPIO | USB PHY U32, pin 27 | Low active USB PHY Reset (pulled-up to PS_1.8V) | 45 | GPIO | J2-160 | user I/O on B2B | |
| 8 | GPIO | SC CPLD bank 2, pin 13 | user I/O (pulled-up to PS_1.8V) | 46 | GPIO | J2-145 | user I/O on B2B | |
| 9 | GPIO | Ethernet PHY U7, pin 16 | Ethernet PHY Reset | 47 | GPIO | J2-147 | user I/O on B2B | |
| 10 | I²C | SCL-line I²C-interface | 1.8V ref. voltage | 48 | GPIO | J2-149 | user I/O on B2B | |
| 11 | I²C | SDA-line I²C-interface | 1.8V ref. voltage | 49 | GPIO | J2-151 | user I/O on B2B | |
| 12 | GPIO | J2-123 | user I/O on B2B | 50 | GPIO | J2-153 | user I/O on B2B | |
| 13 | GPIO | J2-125 | user I/O on B2B | 51 | GPIO | J2-155 | user I/O on B2B | |
| 14 | GPIO | J2-127 | user I/O on B2B | 52 | ETH0 | USB PHY U32, pin 7 | MDC | |
| 15 | GPIO | J2-129 | user I/O on B2B | 53 | ETH0 | USB PHY U32, pin 8 | MDIO |
Table 5: Default MIO Mapping
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The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
I2C Interface
The I²C-interface on the B2B-connector J2 with the pins J2-119 (I2C_33_SCL) and J2-121 (I2C_33_SDA) is operating with the reference voltage PS_3.3V.
Except the RTC, the remaining component's I²C-interfaces are operating with the reference voltage PS_1.8V (voltage level shifting 3.3V ↔ 1.8V via I²C bus repeater U17).
I2C On-board I2C devices are connected to MIO.. and MIO.. which are configured as I2C... by default. I2C addresses for on-board devices are listed in the table below:
| I2C Device | I2C Address | Notes |
|---|
RTC - Real Time Clock
| Zynq-chip U1, bank 500 (PS MIO), pins MIO10 (SCL), MIO11 (SDA) | user programmable | configured as I2C by default |
| Quad programmable PLL clock generator U16: pins 12 (SCL), 19 (SDA) | 0x70 | - |
| MAC Address EEPROM U23, pins 1 (SCL), 3 (SDA) | 0x53 | - |
| SC CPLD U2, bank 2, pins 16 (SDA), 17 (SCL) | user programmable | - |
| RTC, U24 | 0x6F | - |
| RTC RAM, U24 | 0x57 | - |
RTC - Real Time Clock
An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I²C slave address 0x57. RTC IC is supported by An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD on bank 3, pin 4.
LEDs
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D1
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Green
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D2
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Red
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Zynq-Chip (U1), bank 0 (config bank), 'DONE' (pin W9)
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Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured.
This LED will not operate if the SC CPLD can not power up the PL supply voltage.
Boot Process
The Zynq-module TE0745 supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.
The current boot mode will be set by the MIO-pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'.
Following table describes how to set the control lines to configure the desired boot mode:
| Boot Mode | MIO5 (BOOTMODE_1) | MIO4 (BOOTMODE) | MIO3 | Note |
|---|---|---|---|---|
JTAG | 0 | 0 | 0 | - |
| NOR | 0 | 0 | 1 | MIO3 pin is shared with QSPI Flash Memory (QSPI-DQ1) |
| NAND | 0 | 1 | 0 | - |
| QSPI Flash Memory | 1 | 0 | 0 | standard mode in current configuration |
| SD-Card | 1 | 1 | 0 | SD-Card on base board necessary |
Table 9: Selectable boot modes
On-board Peripherals
Processing System (PS) Peripherals
| Name | IC | ID | PS7 | MIO | Notes |
|---|---|---|---|---|---|
| SPI Flash | S25FL256SAGBHI20 | U14 | QSPI0 | MIO1..MIO6 | - |
Table 8: LEDs of the SoC module
Boot Process
The Zynq-module TE0745 supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.
The current boot mode will be set by the MIO0 pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'.
Following table describes how to set the control lines to configure the desired boot mode:
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MIO3
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JTAG
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Table 9: Selectable boot modes
On-board Peripherals
Processing System (PS) Peripherals
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The System Controller CPLD is the central system management unit on the SoC module which generates control signals and evaluates and handles signals like the "Power Good"-signals of the on-board DC-DC converters. Interfaces between the on-board peripherals and the SoC-module are by-passed, forwarded and controlled by the System Controller CPLD.
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Table 10: VCCIO voltages of CPLD banks
Following table describes the interfaces and functionalities established by the System Controller CPLD:
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Table 11: System Controller CPLD functionalities
Clocking
Clock sources
The SoC module has the following sources to be provided with extern reference clock signals and on-board clock oscillators:
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CLKIN_N, CLKIN_P
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MGT_CLK0_P, MGT_CLK0_N
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SiTime SiT8008BI oscillator, U12
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Programmable PLL Clock (Phase-Locked Loop)
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